Multiprocessor system and access right setting method in the multiprocessor system

• US 20080010643A1
• Filed: 07/05/2007
• Published: 01/10/2008
• Est. Priority Date: 07/07/2006
• Status: Abandoned Application

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Inventors: Oohira, Yoshihiro, Suzuki, Hitoshi, Daito, Masayuki
• Application Number:
  US11/822,335
• Publication Number:
  US 20080010643A1
• Time in Patent Office: Days
• US Class Current: 718/102
• CPC Class Codes: G06F 2209/522 Manager
• CPC Class Codes: G06F 9/526 Mutual exclusion algorithms

Abstract

An access of a processor having an access right to a shared resource is affected by the polling operation of a processor having no access right. A multiprocessor system having a plurality of processors, and a shared resource that can be accessed by the plural processors, the multiprocessor system includes a shared bus that connects the plural processors to the shared resource, a mutual exclusion control unit that holds identification information indicating which processor has an access right to the shared resource among the plural processors, and a local bus that connects the mutual exclusion control unit and the plural processors.

Claims

1. A multiprocessor system comprising:

a plurality of processors;

a shared resource capable of being accessed by the plurality of processors;

a shared bus coupled to the plurality of processors and the shared resource;

a mutual exclusion control unit holding identification information indicating which processor has an access right to the shared resource among the plurality of processors; and

a local bus coupled to the mutual exclusion control unit and the plurality of processors.

2. The multiprocessor system according to claim 1,

wherein the mutual exclusion control unit includes a register holding one of unique values associated respectively to the plurality of processors as the identification information.

3. The multiprocessor system according to claim 1,

wherein the mutual exclusion control unit comprises:

a state storage unit storing the identification information;

an accessing processor determination unit specifying a processor which is currently requesting an access right to the shared resource; and

a state determination unit providing the processor which is currently requesting an access right to the shared resource with information indicative of whether the access right is granted or not via the local bus in response to the identification information stored in the state storage unit.

4. The multiprocessor system according to claim 3,

wherein the state storage unit stores information indicating that none of the plurality of processors has the access right to the shared resource, or information indicating which processor has the access right to the shared resource among the plurality of processors.

5. The multiprocessor system according to claim 3,

wherein the mutual exclusion control unit outputs information indicating that the access right is newly acquired, information indicating that the access right has been already acquired, or information indicating that another processor has acquired the access right to the processor that requests the access right on the basis of an output of the state determination unit.

6. The multiprocessor system according to claim 3,

wherein the processor that has acquired the access right to the shared resource among the plurality of processors outputs any one of a write value indicating that the access right is released or maintained to the mutual exclusion control unit when releasing the access right.

7. The multiprocessor system according to claim 6,

wherein the information that is stored in the state storage unit is maintained or changed on the basis of the write value.

8. The multiprocessor system according to claim 3,

wherein the mutual exclusion control unit outputs a signal indicative of an access disenable to the processor that requests the access right to the shared resource in the case where the processor that requests the access right to the shared resource is different from the processor that holds the access right to the shared resource.

9. The multiprocessor system according to claim 1,

wherein the mutual exclusion control unit has a first arbiter that permits an access to the identification information through the local bus with respect to one of the plurality of processors.

10. The multiprocessor system according to claim 9, further comprising:

a second arbiter that gives a use right of the shared bus to one of the plurality of processors upon receiving requests from the plurality of processors.

11. The multiprocessor system according to claim 1, further comprising:

a first arbiter that gives a use right of the local bus to one of the plurality of processors upon receiving requests from the plurality of processors before accessing to the identification information through the local bus.

12. The multiprocessor system according to claim 11, further comprising:

a second arbiter that gives a use right of the shared bus to one of the plurality of processors upon receiving requests from the plurality of processors.

13. The multiprocessor system according to claim 1,

wherein the local bus comprises a plurality of local buses so that the mutual exclusion control unit and the plurality of processors are connected one-on-one.

14. The multiprocessor system according to claim 1,

wherein the local bus is commonly connected to the plurality of processors.

15. An access right setting method of setting an access right to one of a plurality of processors with respect to a shared resource coupled to the plurality of processors via a shared bus, the method comprising:

holding identification information indicating which processor has an access right to the shared resource among the plurality of processors;

receiving a request to acquire an access right to the shared resource from one of the plurality of processors via a local bus;

determining a processor which is currently requesting an access right to the shared resource;

comparing the determination result with the identification information; and

providing the processor which is currently requesting an access right to the shared resource with information indicative of whether the access right is granted or not via the local bus.