SPINTRONIC DEVICES WITH CONSTRAINED SPINTRONIC DOPANT

• US 20080012004A1
• Filed: 03/16/2007
• Published: 01/17/2008
• Est. Priority Date: 03/17/2006
• Status: Abandoned Application

• Current Assignee: Mears Technologies Incorporated
• Original Assignee: Mears Technologies Incorporated
• Inventors: Yiptong, Jean Augustin, Mears, Robert, Dukovski, Ilija, Halilov, Samed, Hytha, Marek, Huang, Xiangyang
• Application Number:
  US11/687,422
• Publication Number:
  US 20080012004A1
• Time in Patent Office: Days
• US Class Current: 257/20
• CPC Class Codes: B82Y 25/00 Nanomagnetism, e.g. magnetoimpedance, anisotropic magnetoresistance, giant magnetoresistance or tunneling magnetoresistance
• CPC Class Codes: H01F 1/402 of II-VI type, e.g. Zn1-x Crx Se
• CPC Class Codes: H01F 1/404 of III-V type, e.g. In1-x Mnx As
• CPC Class Codes: H01F 1/405 of IV type, e.g. Ge1-xMnx
• CPC Class Codes: H01F 10/193 Magnetic semiconductor compounds in general H01F1/40; multilayers, e.g. superlattices H01F10/3213
• CPC Class Codes: H01F 10/325 the spacer being noble metal
• CPC Class Codes: H01L 29/66984 Devices using spin polarized carriers

Abstract

A spintronic device may include at least one superlattice and at least one electrical contact coupled thereto, with the at least one superlattice including a plurality of groups of layers. Each group of layers may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion having a crystal lattice, at least one non-semiconductor monolayer constrained within the crystal lattice of adjacent base semiconductor portions, and a spintronic dopant. The spintronic dopant may be constrained within the crystal lattice of the base semiconductor portion by the at least one non-semiconductor monolayer. In some embodiments, the repeating structure of a superlattice may not be needed.

Claims

1. A spintronic device comprising:

at least one superlattice; and

at least one electrical contact coupled to said at least one superlattice;

said at least one superlattice comprising a plurality of groups of layers with each group of layers comprising

a plurality of stacked base semiconductor monolayers defining a base semiconductor portion having a crystal lattice,

at least one non-semiconductor monolayer constrained within the crystal lattice of adjacent base semiconductor portions, and

a spintronic dopant constrained within the crystal lattice of the base semiconductor portion by said at least one non-semiconductor monolayer.

2. The spintronic device according to claim 1 wherein said spintronic dopant comprises at least one spintronic dopant monolayer adjacent said at least one non-semiconductor monolayer.

3. The spintronic device according to claim 1 wherein said spintronic dopant comprises a transition metal.

4. The spintronic device according to claim 1 wherein said spintronic dopant comprises Manganese.

5. The spintronic device according to claim 1 wherein said at least one transition metal comprises at least one of Manganese, Iron, and Chromium.

6. The spintronic device according to claim 1 wherein said spintronic dopant comprises a rare earth.

7. The spintronic device according to claim 1 wherein said rare earth comprises a rare earth lanthanide.

8. The spintronic device according to claim 1 wherein said non-semiconductor comprises Oxygen.

9. The spintronic device according to claim 1 wherein said non-semiconductor comprises at least one of Oxygen, Nitrogen, Fluorine, Carbon-Oxygen, and Sulphur.

10. The spintronic device according to claim 1 wherein said semiconductor comprises Silicon.

11. The spintronic device according to claim 1 wherein said semiconductor comprises a semiconductor selected from the group comprising Group IV semiconductors, Group III-V semiconductors, and Group II-VI semiconductors.

12. The spintronic device according to claim 1 wherein said at least one superlattice comprises a pair of superlattices;

and further comprising;

a substrate carrying said pair of superlattices in spaced apart relation to define a source and a drain;

a channel between said source and drain; and

a gate adjacent said channel so that said spintronic device defines a spintronic field effect transistor.

13. The spintronic device according to claim 1 wherein said at least one superlattice comprises a pair of superlattices;

and further comprising;

a substrate carrying said pair of superlattices in spaced apart relation; and

a spacer between said pair of superlattices so that said spintronic device defines a spintronic valve.

14. The spintronic device according to claim 1 wherein said at least one superlattice exhibits a Curie temperature of at least as high as room temperature.

15. A spintronic device comprising:

at least one superlattice; and

at least one electrical contact coupled to said at least one superlattice;

said at least one superlattice comprising a plurality of groups of layers with each group of layers comprising

a plurality of stacked base Silicon monolayers defining a base Silicon portion having a crystal lattice,

at least one Oxygen monolayer constrained within the crystal lattice of adjacent base Silicon portions, and

a spintronic dopant constrained within the crystal lattice of the base Silicon portion by said at least one Oxygen monolayer.

16. The spintronic device according to claim 15 wherein said at least one spintronic dopant comprises at least one spintronic dopant monolayer adjacent said at least one non-semiconductor monolayer.

17. The spintronic device according to claim 15 wherein said spintronic dopant comprises at least one of a transition metal, and a rare earth.

18. The spintronic device according to claim 15 wherein said at least one superlattice comprises a pair of superlattices;

and further comprising;

a substrate carrying said pair of superlattices in spaced apart relation to define a source and a drain;

a channel between said source and drain; and

a gate adjacent said channel so that said spintronic device defines a spintronic field effect transistor.

19. The spintronic device according to claim 15 wherein said at least one superlattice comprises a pair of superlattices;

and further comprising;

a substrate carrying said pair of superlattices in spaced apart relation; and

a spacer between said pair of superlattices so that said spintronic device defines a spintronic valve.

20. The spintronic device according to claim 15 wherein said at least one superlattice exhibits a Curie temperature of at least as high as room temperature.

21. A spintronic device comprising:

a plurality of stacked base semiconductor monolayers defining a base semiconductor portion having a crystal lattice;

at least one non-semiconductor monolayer constrained within the crystal lattice;

a spintronic dopant constrained within the crystal lattice of the base semiconductor portion by said at least one non-semiconductor monolayer; and

an electrical contact coupled to said base semiconductor portion.

22. The spintronic device according to claim 21 wherein said spintronic dopant comprises at least one spintronic dopant monolayer adjacent said at least one non-semiconductor monolayer.

23. The spintronic device according to claim 21 wherein said spintronic dopant comprises at least one of a transition metal and a rare earth.

24. The spintronic device according to claim 21 wherein said non-semiconductor comprises at least one of Oxygen, Nitrogen, Fluorine, Carbon-Oxygen, and Sulphur.

25. The spintronic device according to claim 21 wherein said semiconductor comprises a semiconductor selected from the group comprising Group IV semiconductors, Group III-V semiconductors, and Group II-VI semiconductors.

26. The spintronic device according to claim 21 further comprising a substrate carrying said base semiconductor portion.

27. The spintronic device according to claim 21 wherein said base semiconductor portion exhibits a Curie temperature of at least as high as room temperature.