Method of manufacturing semiconductor device having trench-gate transistor

• US 20080012053A1
• Filed: 07/06/2007
• Published: 01/17/2008
• Est. Priority Date: 07/13/2006
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Elpida Memory Incorporated (Micron Technology, Inc.)
• Inventors: Kujirai, Hiroshi
• Granted Patent: US 7,816,208 B2
• Time in Patent Office: Days
• US Class Current: 257/288
• CPC Class Codes: H01L 21/76232 of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls H01L21/76229 takes precedence
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7853 the body having a non-rectangular crossection
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/056 the transistor being a FinFET

Abstract

A method of manufacturing a semiconductor device includes: a first step of forming an STI region and an active region surrounded by the STI region on a semiconductor substrate; a second step of forming a protection film protecting a shoulder part of the STI region in a boundary between the active region and the STI region; a third step of forming a gate trench in the active region so as to leave a part of the semiconductor substrate located between a side surface of the STI region and a side surface of the gate trench; a fourth step of forming a gate insulating film on the side surface of the gate trench; a fifth step of forming a gate electrode, at least a part of the gate electrode being buried in the gate trench; and a sixth step of forming a source region and a drain region in regions located on both sides of the gate trench in an extension direction of the gate trench, respectively, so that the part of the semiconductor substrate functions as a channel region.

Claims

1. A method of manufacturing a semiconductor device, comprising:

a first step of forming an STI (Shallow Trench Isolation) region includes a first insulating film and an active region surrounded by the STI region on a semiconductor substrate so that an upper end of the first insulating film is lapped on an upper end of the active region and so as to include a shoulder part almost perpendicular to the semiconductor substrate in a direction crossing the active region;

a second step of forming a second insulating film and a third insulating film in this order on an entire surface including the shoulder part;

a third step of forming a fourth insulating film on the third insulating film, the fourth insulating film serving as a hard mask when a gate trench is formed;

a fourth step of performing a dry etching using the third insulating film as a stopper, and forming an opening in the fourth insulating film, the opening corresponding to a width of the gate trench;

a fifth step of sequentially removing the third insulating film and the second insulating film exposed to a bottom of the opening; and

a sixth step of forming the gate trench in the semiconductor substrate using the fourth insulating film as a mask in a direction almost parallel to the active region, forming the gate trench using the shoulder part of the STI region as a mask in an extension direction of the gate trench, and leaving a thin film part that is a part of the semiconductor substrate between the gate trench and the STI region.

2. The method of manufacturing the semiconductor device as claimed in claim 1, wherein

the thin film part of the semiconductor substrate includes a surface almost perpendicular to the semiconductor substrate on a side of the gate trench.

3. The method of manufacturing the semiconductor device as claimed in claim 1, wherein

the first insulating film and the third insulating film are silicon oxide films, and the second insulating film and the fourth insulating film are silicon nitride films.

4. The method of manufacturing the semiconductor device as claimed in claim 1, wherein

the forming the gate trench is performed using an etching, which has a high selectivity with respect to both the fourth insulating film and the first insulating film.

5. The method of manufacturing the semiconductor device as claimed in claim 1, further comprising:

a seventh step of forming a thick insulating film on a bottom of the gate trench; and

an eighth step of forming a gate insulating film on a side surface of the gate trench, wherein

the seventh step and the eighth step are performed after the sixth step.

6. The method of manufacturing the semiconductor device as claimed in claim 2, further comprising:

a seventh step of forming a thick insulating film on a bottom of the gate trench; and

an eighth step of forming a gate insulating film on a side surface of the gate trench, wherein

the seventh step and the eighth step are performed after the sixth step.

7. The method of manufacturing the semiconductor device as claimed in claim 3, further comprising:

a seventh step of forming a thick insulating film on a bottom of the gate trench; and

an eighth step of forming a gate insulating film on a side surface of the gate trench, wherein

the seventh step and the eighth step are performed after the sixth step.

8. The method of manufacturing the semiconductor device as claimed in claim 4, further comprising:

a seventh step of forming a thick insulating film on a bottom of the gate trench; and

an eighth step of forming a gate insulating film on a side surface of the gate trench, wherein

the seventh step and the eighth step are performed after the sixth step.

9. The method of manufacturing the semiconductor device as claimed in claim 5, wherein

the seventh step includes

a step of depositing an insulating film at least on the side surface and the bottom of the gate trench by HDP (High Density Plasma)-CVD;

and

a step of removing the insulating film formed on the side surface of the gate trench by wet etching.

10. The method of manufacturing the semiconductor device as claimed in claim 5, wherein

a region under the thick insulating film on the bottom of the gate trench does not serve as a channel region.

11. The method of manufacturing the semiconductor device as claimed in claim 6, wherein

a region under the thick insulating film on the bottom of the gate trench does not serve as a channel region.

12. The method of manufacturing the semiconductor device as claimed in claim 7, wherein

a region under the thick insulating film on the bottom of the gate trench does not serve as a channel region.

13. The method of manufacturing the semiconductor device as claimed in claim 8, wherein

a region under the thick insulating film on the bottom of the gate trench does not serve as a channel region.

14. A method of manufacturing a semiconductor device, comprising:

a first step of forming an STI region and an active region surrounded by the STI region on a semiconductor substrate;

a second step of forming a protection film protecting a shoulder part of the STI region in a boundary between the active region and the STI region;

a third step of forming a gate trench in the active region so as to leave a part of the semiconductor substrate located between a side surface of the STI region and a side surface of the gate trench;

a fourth step of forming a gate insulating film on the side surface of the gate trench;

a fifth step of forming a gate electrode, at least a part of the gate electrode being buried in the gate trench; and

a sixth step of forming a source region and a drain region in regions located on both sides of the gate trench in an extension direction of the gate trench, respectively, so that the part of the semiconductor substrate functions as a channel region.

15. The method of manufacturing the semiconductor device as claimed in claim 14, wherein

a part of the protection film is removed after the second step and before the third step, the part of the protection film being where the gate trench is formed in the third step.

16. The method of manufacturing the semiconductor device as claimed in claim 14, wherein

the protection film includes a plurality of insulating films different in material.

17. The method of manufacturing the semiconductor device as claimed in claim 15, wherein

the protection film includes a plurality of insulating films different in material.

18. The method of manufacturing the semiconductor device as claimed in claim 16, wherein

at least one insulating film of the plurality of insulating film included in the protection film is made of a material different from a material of a mask used at the third step.

19. The method of manufacturing the semiconductor device as claimed in claim 17, wherein

at least one insulating film of the plurality of insulating film included in the protection film is made of a material different from a material of a mask used at the third step.

20. A semiconductor device comprising:

a semiconductor substrate;

an STI region formed in the semiconductor substrate;

a gate trench formed in the semiconductor substrate;

a gate electrode formed in the gate trench; and

a channel region located between a side surface of the STI region and a side surface of the gate trench;

wherein the side surface of the gate trench is almost perpendicular to the semiconductor substrate.