APPARATUS FOR A SELF-ALIGNED RECESSED ACCESS DEVICE (RAD) TRANSISTOR GATE

• US 20080012070A1
• Filed: 09/28/2007
• Published: 01/17/2008
• Est. Priority Date: 07/08/2005
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Juengling, Werner
• Granted Patent: US 8,399,920 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar

Abstract

A method used in fabrication of a recessed access device transistor gate has increased tolerance for mask misalignment. One embodiment of the invention comprises forming a vertical spacing layer over a semiconductor wafer, then etching the vertical spacing layer and the semiconductor wafer to form a recess in the wafer. A conductive transistor gate layer is then formed within the trench and over the vertical spacing layer. The transistor gate layer is etched, which exposes the vertical spacing layer. A spacer layer is formed over the etched conductive gate layer and over the vertical spacing layer, then the spacer layer and the vertical spacing layer are anisotropically etched. Subsequent to anisotropically etching the vertical spacing layer, a portion of the vertical spacing layer is interposed between the semiconductor wafer and the etched conductive transistor gate layer in a direction perpendicular to the plane of a major surface of the semiconductor wafer.

Claims

1. A semiconductor device comprising:

a transistor comprising a conductive transistor gate partially formed within a trench in a semiconductor wafer;

a gate dielectric layer interposed between the conductive transistor gate within the trench and the semiconductor wafer;

first and second vertically oriented conductive transistor gate sidewalls;

a first dielectric spacer along the first vertically oriented conductive transistor gate sidewall and a second dielectric spacer along the second vertically oriented conductive transistor gate sidewall; and

a dielectric vertical spacing layer having an unetched first portion interposed between the conductive transistor gate and the semiconductor wafer, a partially etched second portion interposed between the first dielectric spacer and the semiconductor wafer, and a partially etched third portion interposed between the second dielectric spacer and the semiconductor wafer.

2. The semiconductor device of claim 1 further comprising a pad dielectric layer having a first portion interposed between the partially etched second portion of the dielectric vertical spacing layer and the semiconductor wafer and a second portion interposed between the partially etched third portion of the dielectric vertical spacing layer and the semiconductor wafer.

3. The semiconductor device of claim 1 wherein the unetched first portion of the dielectric vertical spacing layer comprises first and second segments and tile conductive transistor gate is interposed between the first and second segments of the dielectric vertical spacing layer.

4. The semiconductor device of claim 1, wherein:

the first dielectric spacer contacts the unetched first portion of the dielectric vertical spacing layer; and

the second dielectric spacer is free from contact with an unetched portion of the dielectric vertical spacing layer.

5. An electronic device comprising at least one microprocessor and at least one memory device, wherein the at least one memory device comprises:

at least one transistor comprising;

a conductive transistor gate partially formed within a trench in a semiconductor wafer;

a gate dielectric layer interposed between the conductive transistor gate within the trench and the semiconductor wafer;

first and second vertically oriented conductive transistor gate sidewalls;

a first dielectric spacer along the first vertically oriented conductive transistor gate sidewall and a second dielectric spacer along the second vertically oriented conductive transistor gate sidewall; and

a dielectric vertical spacing layer having an unetched first portion interposed between the conductive transistor gate and the semiconductor wafer, a partially etched second portion interposed between the first dielectric spacer and the semiconductor wafer, and a partially etched third portion interposed between the second dielectric spacer and the semiconductor wafer.

6. The electronic device of claim 5 wherein the at least one transistor further comprises a pad dielectric layer having a first portion interposed between the partially etched second portion of the dielectric vertical spacing layer and the semiconductor wafer and a second portion interposed between the partially etched third portion of the dielectric vertical spacing layer and the semiconductor wafer.

7. The electronic device of claim 5, wherein the unetched first portion of the dielectric vertical spacing layer comprises first and second segments and the conductive transistor gate is interposed between the first and second segments of the dielectric vertical spacing layer.

8. The electronic device of claim 5, wherein:

the first dielectric spacer contacts the unetched first portion of the dielectric vertical spacing layer; and

the second dielectric spacer is free from contact with an unetched portion of the dielectric vertical spacing layer.