Field Effect Transistor with Trench Filled with Insulating Material and Strips of Semi-insulating Material Along Trench Sidewalls

• US 20080012071A1
• Filed: 09/27/2007
• Published: 01/17/2008
• Est. Priority Date: 07/18/2002
• Status: Active Grant

• Current Assignee: Peter Wilson, Steven Sapp
• Original Assignee: Peter Wilson, Steven Sapp
• Inventors: Wilson, Peter, Sapp, Steven
• Granted Patent: US 7,977,744 B2
• Time in Patent Office: Days
• US Class Current: 257/341
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/405 Resistive arrangements, e.g. resistive or semi-insulating field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A MOSFET comprises a first semiconductor region having a first surface, a first insulation-filled trench region extending from the first surface into the first semiconductor region, and strips of semi-insulating material along the sidewalls of the first insulation-filled trench region. The strips of semi-insulating material are insulated from the first semiconductor region.

Claims

1. A MOSFET comprising:

a first semiconductor region having a first surface;

a first insulation-filled trench region extending from the first surface into the first semiconductor region; and

strips of semi-insulating material along the sidewalls of the first insulation-filled trench region, the strips of semi-insulating material being insulated from the first semiconductor region.

2. The MOSFET of claim 1 further comprising:

a second insulation-filled trench region extending from the first surface to the predetermined depth in the first semiconductor region, the second insulation-filled trench region having strips of semi-insulating material along its sidewalls, the strips of semi-insulating material being insulated from the first semiconductor region,

wherein the first and second insulation-filled trench regions are spaced apart in the first semiconductor region to form a drift region therebetween, the volume of each of the first and second insulation-filled trench regions being greater than one-quarter of the volume of the drift region.

3. The MOSFET of claim 1 further comprising:

a body region extending from the first surface into the first semiconductor region, the body region being of a conductivity type opposite that of the first semiconductor region;

a source region in the body region, the source region being of the same conductivity type as the first semiconductor region;

a second trench region extending from the first surface into the first semiconductor region; and

a gate in the second trench region extending across a portion of the body region and overlapping the source and the first semiconductor regions such that a channel region extending perpendicularly to the first surface is formed in the body region between the source and first semiconductor regions.

4. The MOSFET of claim 1 further comprising:

first and second body regions each extending from the first surface into the first semiconductor region, the first body region being laterally spaced from the second body region to form a JFET region therebetween, the first and second and body regions being of a conductivity type opposite that of the first semiconductor region; and

first and second source regions in the first and second body regions respectively, the first and second source regions being of the same conductivity type as the first semiconductor region.

5. The MOSFET of claim 4 further comprising a gate extending over but being insulated from the JFET region and a portion of the first and second body regions, and overlapping the first and second source regions such that a channel region is formed along a body surface of each of the first and second body regions between the corresponding source and JFET regions.

6. The MOSFET of claim 4 further comprising:

a gate extending over but being insulated from each of the first and second body regions such that a channel region is formed along a surface of each of the first and second body regions between the corresponding source and JFET regions, the gate being discontinuous over a surface of the JFET region between the first and second body regions.

7. The MOSFET of claim 1 wherein the strips of semi-insulating material are from oxygen-doped polysilicon material.

8. The MOSFET of claim 1 further comprising a source region, wherein the strips of semi-insulating material are electrically connected to the source regions.

9. The MOSFET of claim 1 wherein each of the strips of semi-insulating material is insulated from its surrounding regions.

10. The MOSFET of claim 1 wherein each of the strips of semi-insulating material is floating.

11. The MOSFET of claim 1 further comprising a drain and a source, each of the strips of semi-insulating material being electrically coupled between the drain and the source.

12. The MOSFET of claim 1 further comprising a drain and a source, each of the strips of semi-insulating material being electrically coupled between the drain and the source so that during an operating mode of the MOSFET each of the strips of semi-insulating material acquires a linear voltage gradient from one end of the strip to an opposite end of the strip.

13. The MOSFET of claim 1 wherein:

the first semiconductor region is over and in contact with a second semiconductor region of same conductivity type as the first semiconductor region, the second semiconductor region having higher doping concentration than the first semiconductor region, and

the strips of semi-insulating material extending through the first semiconductor region and terminating in the second semiconductor region.

14. The MOSFET of claim 1 wherein:

the first semiconductor region is over and in contact with a second semiconductor region of same conductivity type as the first semiconductor region, the second semiconductor region having higher doping concentration than the first semiconductor region, and

the first insulation-filled trench extending through the first semiconductor region and terminating in the second semiconductor region.