Silicon-on-insulator semiconductor device

• US 20080012075A1
• Filed: 05/18/2007
• Published: 01/17/2008
• Est. Priority Date: 07/13/2006
• Status: Active Grant

• Current Assignee: Oki Semiconductor Company Limited (ROHM Co., Ltd.)
• Original Assignee: OKI Electric Industry Company Limited
• Inventors: Fukuda, Koichi
• Granted Patent: US 7,514,747 B2
• Time in Patent Office: Days
• US Class Current: 257/347
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/78612 for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor device formed in a silicon-on-insulator substrate includes a silicon channel region located between silicon source and drain regions, and a low-carrier-concentration layer that underlies the channel region. The low-carrier-concentration layer makes contact with both the channel region and the source region. The channel region and the low-carrier-concentration layer are of the same conductive type, but the low-carrier-concentration layer is doped to have a lower carrier concentration than the channel region. The low-carrier-concentration layer eliminates the floating substrate effect, because carriers that would otherwise accumulate in the channel region can escape through the low-carrier-concentration layer into the source region.

Claims

1. A semiconductor device formed in a silicon-on-insulator (SOI) substrate including an insulating layer and a semiconductor layer disposed on the insulating layer, the semiconductor device including a gate electrode, a gate insulation film sandwiched between the gate electrode and the semiconductor layer, and a source region and a drain region of a first conductive type formed in the semiconductor layer on mutually opposite sides of the gate electrode, the source region and the drain region having a first carrier concentration, wherein the semiconductor layer comprises:

a channel region of a second conductive type opposite to the first conductive type, the channel region being disposed below the gate electrode, the channel region being doped to have a second carrier concentration; and

a low-carrier-concentration layer of the second conductive type disposed partly below the channel region, making contact with the source region and the channel region, the low-carrier-concentration layer being doped to have a third carrier concentration lower than the second carrier concentration.

2. The semiconductor device of claim 1, wherein the low-carrier-concentration layer is an unchanged part of the semiconductor layer remaining after formation of the channel region and the source region.

3. The semiconductor device of claim 1, wherein the low-carrier-concentration layer is a doubly doped layer doped with an impurity of the first conductive type and another impurity of the second conductive type.

4. The semiconductor device of claim 1, wherein the third carrier concentration is greater than zero but less than 1×

10¹⁷/cm³.

5. The semiconductor device of claim 4, wherein the third carrier concentration is substantially 1×

10¹⁴/cm³.

6. The semiconductor device of claim 4, wherein the second carrier concentration is at least 1×

10¹⁷/cm³

7. The semiconductor device of claim 4, wherein the second carrier concentration is not more than 5×

10¹⁸/cm³.

8. The semiconductor device of claim 1, wherein the low-carrier-concentration layer and the source region are electrically separated by an energy barrier not exceeding 0.9 electron volts.

9. The semiconductor device of claim 8, wherein the low-carrier-concentration layer and the source region are electrically separated by an energy barrier of at least 0.6 electron volts.

10. The semiconductor device of claim 1, further comprising a pocket layer of the second conductive type disposed in contact with the low-carrier-concentration layer, the drain region, and the channel region, the pocket layer being doped to have a fourth carrier concentration higher than the second carrier concentration.

11. The semiconductor device of claim 10, wherein the fourth carrier concentration is at least 1×

10¹⁸/cm³.

12. The semiconductor device of claim 1, wherein the source region includes an extension with a fifth carrier concentration lower than the first carrier concentration, the semiconductor device including a first pn junction between the source region and the channel region, the pn junction being formed at an interface between the channel region and the extension of the source region.

13. The semiconductor device of claim 12, wherein the low-carrier-concentration layer occupies space between the channel region and the insulating layer and space between the extension of the source region and the insulating layer.

14. The semiconductor device of claim 1, wherein the silicon-on-insulator substrate includes a silicon supporting layer, the insulating layer being disposed the silicon supporting layer and the semiconductor layer

15. The semiconductor device of claim 14, wherein the insulating layer is a buried oxide layer.

16. The semiconductor device of claim 1, wherein the source region extends from a surface of the semiconductor layer to the insulating layer.

17. The semiconductor device of claim 1, wherein the source region includes a metal silicide layer.