STRUCTURE OF CAPACITOR SET AND METHOD FOR REDUCING CAPACITANCE VARIATION BETWEEN CAPACITORS

• US 20080012092A1
• Filed: 07/04/2006
• Published: 01/17/2008
• Est. Priority Date: 07/04/2006
• Status: Active Grant

• Current Assignee: Marlin Semiconductor Limited (f/k/a Sandyford Semiconductor Limited) (Vector Capital Corporation)
• Original Assignee: United Microelectronics Corporation
• Inventors: Fan, Cheng-Wen, Liang, Victor-Chiang, Ko, Chun-Yao, Chiang, Yu-Ho, Tzeng, Chih-Yuh, Yang, Chien-Kuo, Tseng, Hua-Chou
• Granted Patent: US 8,133,792 B2
• Time in Patent Office: Days
• US Class Current: 257/532
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 28/87 made by depositing layers, e.g. by depositing alternating conductive and insulating layers
• CPC Class Codes: H01L 28/91 made by depositing layers, e.g. by depositing alternating conductive and insulating layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A structure of a capacitor set is described, including at least two capacitors that are disposed at the same position on a substrate and include a first capacitor and a second capacitor. The first capacitor includes multiple first capacitor units electrically connected with each other in parallel. The second capacitor includes multiple second capacitor units electrically connected with each other in parallel. The first and the second capacitor units are arranged spatially intermixing with each other to form an array.

Claims

1. A structure of a capacitor set, comprising at least two capacitors disposed at the same position on a substrate, wherein the two capacitors comprise:

a first capacitor, comprising a plurality of first capacitor units electrically connected with each other in parallel; and

a second capacitor, comprising a plurality of second capacitor units electrically connected with each other in parallel,

wherein the first and the second capacitor units are arranged spatially intermixing with each other to form an array.

2. The structure of claim 1, wherein the first and the second capacitor units are arranged in a two-dimensional (2D) array in one plane.

3. The structure of claim 2, wherein the plane is parallel or perpendicular to a surface of the substrate.

4. The structure of claim 1, wherein the first and the second capacitor units are arranged in a three-dimensional (3D) array.

5. The structure of claim 4, wherein the first and the second capacitor units are arranged alternately in a first and a second dimensional directions of the 3D array but repeatedly in a third dimensional direction of the 3D array.

6. The structure of claim 5, wherein the first and the second dimensional directions are parallel to a surface of the substrate, and the third dimensional direction is perpendicular to the surface of the substrate.

7. The structure of claim 5, wherein the first and the third dimensional directions are parallel to a surface of the substrate, and the second dimensional direction is perpendicular to the surface of the substrate.

8. The structure of claim 4, wherein the first and the second capacitor units are arranged alternately in each of three dimensional directions of the 3D array.

9. The structure of claim 8, wherein the three dimensional directions are perpendicular to each other and include two directions parallel to a surface of the substrate and one direction perpendicular to the surface of the substrate.

10. The structure of claim 1, wherein the first capacitor units and the second capacitor units are the same in number and in capacitance per capacitor unit.

11. The structure of claim 1, wherein the first and the second capacitors comprise MOM capacitors or MIM capacitors.

12. The structure of claim 1, wherein

each of the first capacitor units comprises a first electrode, a second electrode and a dielectric material between the first and the second electrodes;

each of the second capacitor units comprises a third electrode, a fourth electrode and the dielectric material between the third and the fourth electrodes;

in the first capacitor units, all of the first electrodes are electrically connected with each other and all of the second electrodes are electrically connected with each other; and

in the second capacitor units, all of the third electrodes are electrically connected with each other and all of the fourth electrodes are electrically connected with each other.

13. The structure of claim 12, wherein the first and the second capacitors comprise MOM capacitors, and each of the first to fourth electrodes has a comb-like structure.

14. A method for reducing capacitance variations of capacitors, comprising:

forming at least a first and a second capacitors at the same position on a substrate, comprising;

forming a plurality of first capacitor units electrically connected with each other in parallel and a plurality of second capacitor units electrically connected with each other in parallel to respectively constitute the first capacitor and the second capacitor, wherein

the first capacitor units and the second capacitor units are the same in number and in capacitance per capacitor unit, and are arranged spatially intermixing with each other to form an array.

15. The method of claim 14, wherein the first and the second capacitor units are arranged in a two-dimensional (2D) array in one plane.

16. The method of claim 15, wherein the one plane is parallel or perpendicular to a surface of the substrate.

17. The method of claim 14, wherein the first and the second capacitor units are arranged in a three-dimensional (3D) array.

18. The method of claim 17, wherein the first and the second capacitor units are arranged alternately in a first and a second dimensional directions of the 3D array but repeatedly in a third dimensional direction of the 3D array.

19. The method of claim 18, wherein the first and the second dimensional directions are parallel to a surface of the substrate, and the third dimensional direction is perpendicular to the surface of the substrate.

20. The method of claim 18, wherein the first and the third dimensional directions are parallel to a surface of the substrate, and the second dimensional direction is perpendicular to the surface of the substrate.

21. The method of claim 17, wherein the first and the second capacitor units are arranged alternately in each of three dimensional directions of the 3D array.

22. The method of claim 21, wherein the three dimensional directions are perpendicular to each other and include two directions parallel to a surface of the substrate and one direction perpendicular to the surface of the substrate.

23. The method of claim 14, wherein the first and the second capacitors comprise MOM capacitors.

24. The method of claim 14, wherein the first and the second capacitors comprise MIM capacitors.

25. The method of claim 14, wherein

each of the first capacitor units comprises a first electrode, a second electrode and a dielectric material between the first and the second electrodes;

each of the second capacitor units comprises a third electrode, a fourth electrode and the dielectric material between the third and the fourth electrodes;

in the first capacitor units, all of the first electrodes are electrically connected with each other and all of the second electrodes are electrically connected with each other; and

in the second capacitor units, all of the third electrodes are electrically connected with each other and all of the fourth electrodes are electrically connected with each other.

26. The method of claim 25, wherein the first and the second capacitors comprise MOM capacitors, and each of the first to fourth electrodes has a comb-like structure.