Amplifier employing interleaved signals for PWM ripple suppression

• US 20080012539A1
• Filed: 07/12/2006
• Published: 01/17/2008
• Est. Priority Date: 07/12/2006
• Status: Active Grant

• Current Assignee: Harman International Industries Incorporated (Samsung Electronics Co. Ltd.)
• Original Assignee: Harman International Industries Incorporated (Samsung Electronics Co. Ltd.)
• Inventors: Stanley, Gerald R.
• Granted Patent: US 7,598,714 B2
• Time in Patent Office: Days
• US Class Current: 323/222
• CPC Class Codes: H03F 1/32 Modifications of amplifiers to reduce non-linear distortion by negative feedback H03F1/34
• CPC Class Codes: H03F 3/2173 of the bridge type
• CPC Class Codes: H03K 17/16 Modifications for eliminating interference voltages or currents
• CPC Class Codes: H03K 2217/0036 Means reducing energy consumption
• CPC Class Codes: H03K 7/08 Duration or width modulation ; Duty cycle modulation

Abstract

An amplifier having improved distortion characteristics is set forth. The amplifier includes an interleaved PWM amplifier that generates interleaved PWM pulses in response to a modified input signal and one or more carrier signals. The interleaved PWM pulses of the amplifier are used to drive a power stage, such as an opposed current power stage. The amplifier also includes an interleaved PWM generator that provides interleaved PWM pulses in response to the modified input signal and one or more further carrier signals. The carrier signals used by the PWM generator may differ in phase from the carrier signals used by the interleaved PWM amplifier to generate its interleaved PWM pulses. One or more feedback circuits are employed in the generation of the modified input signal. More particularly, the feedback circuit(s) generates the modified input signal based on an input signal that is to be amplified and the interleaved PWM pulses of the interleaved PWM generator.

Claims

1. An amplifier comprising:

an interleaved PWM amplifier generating interleaved PWM pulses in response to a modified input signal and one or more carrier signals to drive a power stage of the interleaved PWM amplifier;

an interleaved PWM generator providing interleaved PWM pulses in response to the modified input signal and one or more further carrier signals; and

one or more feedback circuits responsive to an input signal and the interleaved PWM pulses of the interleaved PWM generator to generate the modified input signal.

2. An amplifier as claimed in claim 1, where though one or more further carrier signals differ in phase from the one or more carrier signals used by the interleaved PWM amplifier to generate its interleaved PWM pulses.

3. An amplifier as claimed in claim 1, where the one or more feedback circuits comprise:

a first feedback circuit disposed to feedback an output of the power stage of the interleaved amplifier to generate a first feedback signal;

a second feedback circuit disposed to feedback the interleaved PWM pulses of the PWM generator to generate a second feedback signal;

a combiner circuit disposed to combine the input signal, the first feedback signal, and the second feedback signal to generate the modified input signal.

4. An amplifier as claimed in claim 3, where the interleaved PWM amplifier and the first feedback circuit combine to exhibit a first signal transfer characteristic, where the interleaved PWM generator and the second feedback circuit combine to exhibit a second signal transfer characteristic, where the first and second transfer characteristics are proportional to one another in about the same ratio as N_L to N_N over at least a predetermined portion of an output bandwidth of the amplifier, and where N_L is the interleave order of the interleaved PWM generator and N_N is the interleave order of the interleaved PWM amplifier.

5. An amplifier as claimed in claim 1, where the interleaved PWM amplifier has an interleave order of one.

6. An amplifier comprising:

an interleaved PWM amplifier of interleave order N_N>

1, where the interleaved amplifier generates interleaved PWM pulses in response to a modified input signal and one or more carrier signals to drive a power stage of the interleaved PWM amplifier;

an interleaved PWM generator of interleave order N_L>

1, where the interleaved PWM generator provides interleaved PWM pulses in response to the modified input signal and one or more further carrier signals;

one or more feedback circuits combining an input signal and the interleaved PWM pulses of the interleaved PWM generator to generate the modified input signal.

7. An amplifier as claimed in claim 6, where the one or more further carrier signals provided to the interleaved PWM generator differ in phase from the one or more carrier signals provided to the interleaved amplifier.

8. An amplifier as claimed in claim 6, where N_N and N_L are even integers.

9. An amplifier as claimed in claim 6, where N_N=2 and N_L=2.

10. An amplifier as claimed in claim 6, where the one or more feedback circuits comprise:

a first feedback circuit disposed to feedback an output of the power stage of the interleaved amplifier to generate a first feedback signal;

a second feedback circuit disposed to feedback the interleaved PWM pulses of the PWM generator to generate a second feedback signal;

a combiner circuit disposed to combine the input signal, the first feedback signal, and the second feedback signal to generate the modified input signal.

11. An amplifier as claimed in claim 10, where the interleaved PWM amplifier and the first feedback circuit combine to exhibit a first signal transfer characteristic, where the interleaved PWM generator and the second feedback circuit combine to exhibit a second signal transfer characteristic, and where the first and second transfer characteristics are proportional to one another in about the same ratio as N_L to N_N over at least a predetermined portion of an output bandwidth of the amplifier.

12. An amplifier as claimed in claim 11, where N_N&

N_L are even integers.

13. An amplifier as claimed in claim 11, where N_N=2 and N_L=2.

14. An amplifier comprising:

a carrier generator circuit providing at least first and second carrier output signals;

at least one pulse width modulator generating an interleaved pulse output drive signal in response to the first carrier output signal and a modified input signal;

at least one opposed current output driver responsive to the interleaved pulse output drive signal of the at least one pulse width modulator to generate a load signal for use in driving a load;

a feedback summing circuit responsive to first and second secondary feedback signals to generate the modified input signal to the at least one pulse width modulator;

a first feedback circuit disposed to feed back at least a portion of the load signal as the first feedback signal of the feedback summing circuit;

at least one further pulse width modulator generating a further interleaved pulse output signal in response to the second carrier output signal and the modified input signal;

a second feedback circuit disposed to feed back at least a portion of the further interleaved pulse output signal as the second feedback signal of the feedback summing circuit.

15. An amplifier as claimed in claim 14, where the first and second carrier output signals differ from one another in phase.

16. An amplifier comprising:

an interleaved amplifier section receiving a modified input signal and providing an amplified output signal, where the interleaved amplifier section has a transfer characteristic G_N corresponding to a first set of one or more phasing vectors;

an interleaved PWM section receiving the modified input signal and providing an interleaved pulse output signal, where the interleaved PWM section has a transfer characteristic G_L corresponding to a second set of one or more phasing vectors that are different from the first set of one or more phasing vectors;

a summer circuit;

a feedback circuit disposed to feedback at least a portion of the amplified output signal of the interleaved amplifier section to the summer circuit, where the feedback circuit has a transfer characteristic H_N;

a further feedback circuit disposed to feedback at least a portion of the interleaved pulse output signal of the interleaved PWM section to the summer circuit, where the feedback circuit has a transfer characteristic H_L; and

where the combiner circuit generates the modified input signal by subtracting the output signal of the feedback circuit and the output signal of the further feedback circuit from an input signal that is to be amplified.

17. An amplifier as claimed in claim 16, where G_L·

H_L is nominally proportional to G_N·

H_N over at least a predetermined portion of an output bandwidth of the amplifier.

18. An amplifier as claimed in claim 17, where transfer characteristic G_N corresponds to an interleave order of N_N and transfer characteristic G_L corresponds to an interleave order of N_L, and where the proportionality of G_L·

H_L to G_N·

H_N is about N_L to N_N.

19. An amplifier as claimed in claim 16, where the first set of phasing vectors are disposed at angles with one another to equally divide a circle.

20. An amplifier as claimed in claim 16, where the second set of phasing vectors are disposed at angles with one another to equally divide a circle.

21. An amplifier as claimed in claim 19, where the second set of phasing vectors equally divide a circle at angles offset from the first set of phasing vectors.

22. An amplifier as claimed in claim 19, where the first and second set of phasing vectors combine to equally divide a circle.

23. An amplifier comprising:

an interleaved amplifier section receiving a modified input signal and providing an amplified output signal, where the interleaved amplifier section has a transfer characteristic G_N;

a signal attenuator disposed to provide an attenuated output signal corresponding to the amplified output signal from the interleaved amplifier section;

an interleaved PWM section receiving the modified input signal and providing an interleaved pulse output signal, where the interleaved PWM section has a transfer characteristic G_L, and where the interleaved pulse output signal is generated using one or more further carrier signals;

a delay circuit disposed to provide a delayed output signal corresponding to the interleaved pulse output signal of the interleaved PWM section;

one or more combiner circuits generating the modified input signal based on the delayed output signal, the attenuated output signal, and an input signal that corresponds to a signal that is to be amplified.

24. An amplifier as claimed in claim 23, where the one or more further carrier signals differ in phase from the one or more carrier signals used by the interleaved amplifier section.

25. An amplifier as claimed in claim 23, where the one or more carrier signals used by the interleaved PWM section corresponds to a first set of phasing vectors, and where the first set of phasing vectors are disposed at angles with one another to equally divide a circle.

26. An amplifier as claimed in claim 23, where the one or more carrier signals used by the interleaved amplifier correspond to a second set of phasing vectors, and where the second set of phasing vectors are disposed at angles with one another to equally divide a circle.

27. An amplifier as claimed in claim 26, where the second set of phasing vectors equally divide a circle at angles offset from the first set of phasing vectors.

28. An amplifier as claimed in claim 26, where the first and second set of phasing vectors combine to equally divide a circle.

29. An amplifier as claimed in claim 23, where the one or more combiner circuits comprises a first combiner circuit generating a feedback signal as a sum of the attenuated output signal and the delayed output signal, and a second combiner circuit subtracting the feedback signal from the input signal.

30. An amplifier as claimed in claim 29, further comprising a processing circuit disposed to process the feedback signal from the first combiner circuit, where the processed feedback signal is provided to the second combiner circuit.

31. An amplifier as claimed in claim 23, where the delay circuit is implemented in the interleaved PWM section and included in the transfer characteristic G_L.

32. A method for operating an amplifier, the method comprising:

generating primary interleaved PWM pulses in response to a modified input signal and one or more carrier signals;

driving a power stage using the primary interleaved PWM pulses;

generating secondary interleaved PWM pulse signals in response to the modified input signal and one or more further carrier signals; and

generating the modified input signal from an input signal and the secondary interleaved PWM pulses.

33. A method for operating an amplifier as claimed in claim 32, where the one or more further carrier signals used to generate the secondary interleaved PWM pulse signals differ in phase from the one or more carrier signals used to generate the primary interleaved PWM pulse signals.

34. A method for operating an amplifier as claimed in claim 32, where the one or more carrier signals used to generate the primary interleaved PWM pulses have corresponding phasing vectors that are equal in magnitude and that equally divide a unit circle.

35. A method for operating an amplifier as claimed in claim 32, where the one or more further carrier signals used to generate the secondary interleaved PWM pulses have corresponding phasing vectors that are equal in magnitude and that equally divide a unit circle.

36. A method for operating an amplifier as claimed in claim 35, where the one or more further carrier signals used to generate the secondary interleaved PWM pulses have corresponding phasing vectors that are equal in magnitude and that equally divide a unit circle at an angle offset to the one or more carrier signals used to generate the primary interleaved PWM pulses.

37. A method for operating an amplifier as claimed in claim 35, where the one or more carrier signals and the one or more further carrier have corresponding phasing vectors that equally divide a unit circle.

38. An amplifier comprising:

an interleaved PWM generator providing primary and secondary sets of interleaved PWM pulses in response to an input signal;

an interleaved PWM output stage responsive to corrected interleaved PWM pulses corresponding to the primary set of interleaved PWM pulses to generate amplified PWM output pulses;

an interleaved PWM corrector responsive to one or more correction signals derived from one or more feedforward signals corresponding to the secondary set of interleaved PWM pulses to generate the corrected interleaved PWM pulses for use by the interleaved PWM output stage.

39. An amplifier as claimed in claim 38, where the interleaved PWM pulses of the primary set are generated with carrier signals that differ in phase from carrier signals used to generate the interleaved PWM pulses of the secondary set

40. An amplifier as claimed in claim 38 where the interleaved PWM corrector is further responsive to one or more feedback signals corresponding to the amplified PWM output pulses to generate the corrected interleaved PWM pulses for use by the interleaved PWM output stage.

42. An amplifier as claimed in claim 40 where the primary set of interleaved PWM pulses is of an interleave order N>

1, the secondary set of interleaved PWM pulses is of an interleave order L, and where N=L.

43. An amplifier comprising:

an interleaved PWM generator providing primary and secondary sets of interleaved PWM pulses in response to an input signal;

a feedforward circuit providing one or more feedforward signals derived from the secondary set of interleaved PWM pulses;

an interleaved PWM output stage responsive to corrected interleaved PWM pulses corresponding to the primary set of interleaved PWM pulses to generate amplified PWM output pulses;

a feedback circuit providing one or more feedback signals derived from the amplified PWM output pulses;

an interleaved PWM corrector responsive to one or more correction signals derived from the one or more feedforward signals and the one or more feedback signals to generate the corrected interleaved PWM pulses for use by the interleaved PWM output stage.

41. An amplifier as claimed in claim 43 where the primary set of interleaved PWM pulses has an interleave order of N>

1, the secondary set of interleaved PWM pulses has an interleave order of L, and where N=L.

44. An amplifier as claimed in claim 43, where the interleaved PWM pulses of the primary set are generated from carrier signals that differ in phase from carrier signals used to generate the interleaved PWM pulses of the secondary set

45. An amplifier as claimed in claim 43 where the primary set of interleaved PWM pulses is of an interleave order N, the secondary set of interleaved PWM pulses is of an interleave order L, and where N=L.

46. An amplifier as claimed in claim 43 where the feedforward circuit comprises:

a converter disposed to receive the secondary set of interleaved PWM pulses; and

a gain circuit having a transfer function H_L.

47. An amplifier as claimed in claim 45 where the feedback circuit comprises a gain circuit having a transfer function H_N.

48. An amplifier as claimed in claim 47 and further comprising a summing circuit that provides one or more summed output signals corresponding to a difference between one or more signals provided at an output of the gain circuit of the feedback circuit and one or more signals provided at an output of the gain circuit of the feedforward circuit.

49. An amplifier as claimed in claim 48 and further comprising a signal processing circuit responsive to the summed output signal to provide the one or more correction signals to the interleaved PWM corrector.