Method and system for trimming voltage or current references

• US 20080012596A1
• Filed: 07/17/2006
• Published: 01/17/2008
• Est. Priority Date: 07/17/2006
• Status: Active Grant

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Qimonda North America Corporation (Infineon Technologies AG)
• Inventors: Lewison, Richard, Hummler, Klaus, Acierno, Vincent
• Granted Patent: US 7,423,445 B2
• Time in Patent Office: Days
• US Class Current: 324/765
• CPC Class Codes: G01R 31/31703 Comparison aspects, e.g. signature analysis, comparators concerning scan tests G01R31/318566; concerning testers G01R31/3193
• CPC Class Codes: G01R 31/31924 Voltage or current aspects, e.g. driver, receiver
• CPC Class Codes: G01R 31/31932 Comparators
• CPC Class Codes: G11C 29/021 in voltage or current generators
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence

Abstract

Trim codes are determined for semiconductor devices under test (DUTs), wherein the trim codes correspond to voltage or current reference value adjustments that cause the DUTs to generate desired voltage or current reference values. The technique involves supplying respective trim codes simultaneously to the DUTs to cause them to generate trimmed analog voltage or current references, simultaneously feeding a test analog voltage or current reference having a preselected reference value to the DUTs, and for each DUT, comparing the value of the test analog reference to the values of the trimmed analog references to ascertain the crossing of the value of the test analog reference by the values of the trimmed references, whereby for each DUT the trim code corresponding to the value of the trimmed analog voltage or current reference immediately above or below the crossing is established as the preferred trim code to be used for that DUT.

Claims

1. A method of determining for each of a plurality of semiconductor devices under test (DUTs) which of a plurality of trim codes corresponding to voltage or current reference value adjustments is the preferred trim code to be used to cause the respective DUTs to provide voltage or current references having a preselected trimmed voltage or current value, comprising:

generating and successively feeding respective trim codes simultaneously to said plurality of DUTs to cause them to generate trimmed analog reference voltages or currents;

feeding a test analog voltage or current reference having a value corresponding to said preselected trimmed reference voltage or current value simultaneously to said plurality of DUTs; and

for each DUT, comparing the value of said test analog voltage or current reference to the values of said trimmed analog voltage or current references to ascertain the crossing of the value of said test analog voltage or current reference by the values of said trimmed analog voltage or current references, whereby for each DUT the trim code corresponding to the value of the trimmed voltage or current reference immediately above or immediately below the crossing is established as the preferred trim code to be used for that DUT.

2. The method of claim 1 further comprising accessing said plurality of DUTs simultaneously to obtain the preferred trim code established for each DUT.

3. The method of claim 1 further comprising storing the preferred trim code established for each DUT.

4. The method of claim 3 wherein the preferred trim code established for each DUT is stored in that DUT.

5. The method of claim 1 wherein comparing of the value of the test analog voltage or current reference to the values of said trimmed analog voltage or current references is performed at each DUT.

6. A system for determining for each of a plurality of semiconductor devices under test (DUTs) which of a plurality of trim codes corresponding to voltage or current reference value adjustments is the preferred trim code to be used to cause the respective DUTs to provide voltage or current references having a preselected trimmed voltage or current value, comprising:

a tester having a plurality of output lines in parallel configuration for feeding respective trim codes generated by the tester simultaneously to said plurality of DUTs to cause them to generate trimmed analog voltage or current references, and also having a plurality of output lines in parallel configuration for feeding a test analog voltage or current reference generated by the tester having a value corresponding to said preselected trimmed voltage or current value simultaneously to said plurality of DUTs;

a comparator for each DUT which compares the value of said test analog voltage or current reference to the values of said trimmed analog voltage or current references to ascertain the crossing of the value of said test analog reference voltage or current reference by the values of said trimmed voltage or current references; and

decision logic which establishes for each DUT either the trim code corresponding to the value of the trimmed analog voltage or current reference immediately above or immediately below the crossing as the preferred trim code to be used for that DUT.

7. The system of claim 6 wherein said comparator for each DUT is physically incorporated in that DUT.

8. The system of claim 7 wherein the preferred trim code established for each DUT is stored in that DUT.

9. The system of claim 6 further comprising a conductor between each DUT and the tester for simultaneously obtaining at the tester the preferred trim code established for each DUT.

10. The system of claim 9 wherein the comparator includes a latch.

11. An integrated circuit device which is capable of providing a voltage or current reference which may be trimmed by a trim code which can be stored in the device, comprising:

a generator responsive to a sequence of trim codes which correspond to voltage or current reference value adjustments for providing a corresponding sequence of trimmed analog voltage or current reference values; and

a comparator to which both said sequence of trimmed analog voltage or current reference values and a test analog voltage or current reference value corresponding to a preselected trimmed voltage or current reference value are provided as inputs, wherein the comparator ascertains the crossing of the value of said test analog voltage or current reference values by said sequence of trimmed analog voltage or current reference values.

12. The device of claim 11 further comprising integrated logic circuitry for establishing either the trim code corresponding to the value of the trimmed analog voltage or current reference immediately above or immediately below the crossing as a preferred trim code which is to be stored in the device.

13. The device of claim 12 wherein the generator provides said trimmed analog voltages or current references such that the values are either in monotonic ascending or monotonic descending order.

14. The device of claim 13 wherein the integrated logic circuitry inhibits the generation of trimmed analog voltage or current references after the preferred trim code which is to be stored in the device is established.

15. The device of claim 14 wherein the comparator includes a latch.

16. A system for determining for each of a plurality of semiconductor devices under test (DUTs) which of a plurality of trim codes corresponding to voltage or current reference value adjustments is the preferred trim code to be used to cause the respective DUTs to provide voltage or current references having a preselected trimmed voltage or current value, comprising:

means for generating and successively feeding respective trim codes simultaneously to said plurality of DUTs to cause them to generate trimmed voltage or current references;

means for feeding a test analog voltage or current reference having a value corresponding to said preselected trimmed reference voltage or current value simultaneously to said plurality of DUTs;

means for comparing for each DUT the value of said test analog voltage or current reference to the values of said trimmed voltage or current references to ascertain the crossing of the value of said test analog voltage or current reference by the values of said trimmed voltage or current references; and

means for establishing for each DUT either the trim code corresponding to the value of the trimmed voltage or current reference either immediately above or immediately below the crossing as the preferred trim code to be used for that DUT.

17. The system of claim 16 wherein said means for comparing and said means for establishing are physically incorporated in the respective DUTs.

18. The system of claim 17 further comprising means for storing the trim code established for each DUT.

19. The system of claim 16 further comprising means for accessing said plurality of DUTs simultaneously to obtain the trim code established for each DUT.

20. The system of claim 19 further comprising means for inhibiting the latching of trim codes by the DUTs after the preferred trim code is established.

21. A system for determining for each of a plurality of semiconductor devices under test (DUTs) which of a plurality of trim codes corresponding to voltage or current reference value adjustments is the preferred trim code to be used to cause the respective DUTs to provide voltage or current references having a preselected trimmed voltage or current value, comprising:

a tester having a plurality of output lines in parallel configuration for feeding respective trim codes generated by the tester simultaneously to said plurality of DUTs and also having a plurality of output lines in parallel configuration for feeding a test analog voltage or current reference generated by the tester having a value corresponding to said preselected trimmed voltage or current value simultaneously to said plurality of DUTs;

a generator for each DUT responsive to said trim codes for providing trimmed analog voltage or current references having values corresponding to said trim codes;

a comparator for each DUT which compares the value of said test analog voltage or current reference to the values of said trimmed analog voltage or current references to ascertain the crossing of the value of said test analog voltage or current reference by the values of said trimmed voltage or current references; and

decision logic which establishes for each DUT either the trim code corresponding to the value of the trimmed analog voltage or current reference immediately above or immediately below the crossing as the preferred trim code to be used for that DUT.

22. The system of claim 21 wherein the generator provides said trimmed analog voltages or current references such that the values are either in monotonic ascending or monotonic descending order.

23. The system of claim 22 wherein the decision logic inhibits the generation of trimmed analog voltage or current references after the preferred trim code is established.

24. The system of claim 23 wherein each comparator includes a latch.

25. The system of claim 24 wherein the decision logic includes an exclusive OR type gate.