Low Cost High Density Rectifier Matrix Memory

• US 20080013354A1
• Filed: 07/20/2007
• Published: 01/17/2008
• Est. Priority Date: 06/22/2000
• Status: Active Grant

• Current Assignee: Western Digital Technologies Incorporated (Western Digital Corporation)
• Original Assignee: Contour Semiconductor, Inc.
• Inventors: Shepard, Daniel
• Granted Patent: US 7,593,246 B2
• Time in Patent Office: Days
• US Class Current: 365/51
• CPC Class Codes: G06K 5/04 Verifying the alignment of markings
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 2029/5006 Current
• CPC Class Codes: G11C 29/006 at wafer scale level, i.e. wafer scale integration [WSI]
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/025 in signal lines
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 7/00 Arrangements for writing information into, or reading information out from, a digital store G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 27/10 including a plurality of individual components in a repetitive configuration
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass

Abstract

A high density memory device is fabricated three dimensionally in layers. To keep points of failure low, address decoding circuits are included within each layer so that, in addition to power and data lines, only the address signal lines need be interconnected between the layers.

Claims

1-11. -11. (canceled)

12. An electronic memory device comprising a plurality of layers of memory circuitry, wherein each layer of memory circuitry comprises a plurality of programmable storage locations and at least one programmable storage location in at least one layer of memory circuitry comprises a phase-change material.

13. The electronic memory device of claim 12, wherein the phase-change material comprises a chalcogenide.

14. An electronic memory device comprising:

a plurality of row storage lines;

a plurality of column storage lines overlapping the plurality of row storage lines;

a plurality of storage locations, wherein each storage location is disposed proximate to a point of intersection between a row storage line and a column storage line; and

a plurality of nonlinear storage elements, wherein each nonlinear storage element is disposed at a storage location,

wherein at least one nonlinear storage element comprises a phase-change material.

15. The electronic memory device of claim 14, wherein the phase-change material comprises a chalcogenide.

16. The electronic memory device of claim 14, wherein each nonlinear storage element comprises a diode.

17. An electronic memory device comprising:

a plurality of layers of memory circuitry, wherein each layer of memory circuitry comprises a plurality of storage locations; and

a first memory controller disposed beneath the plurality of layers of memory circuitry and interconnected to at least one of the layers of memory circuitry.

18. The electronic memory device of claim 17, further comprising a second memory controller disposed beneath the plurality of layers of memory circuitry and interconnected to at least one of the layers of memory circuitry.