Method of making non-volatile memory cell with embedded antifuse

• US 20080013364A1
• Filed: 06/28/2007
• Published: 01/17/2008
• Est. Priority Date: 12/19/2002
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Herner, S., Kumar, Tanmay
• Granted Patent: US 7,660,181 B2
• Time in Patent Office: Days
• US Class Current: 365/148
• CPC Class Codes: G11C 11/00 Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor G11C14/00 - G11C21/00 take precedence
• CPC Class Codes: G11C 11/39 using thyristors or the avalanche or negative resistance type, e.g. PNPN, SCR, SCS, UJT
• CPC Class Codes: G11C 11/5692 read-only digital stores using storage elements with more than two stable states
• CPC Class Codes: G11C 17/06 using diode elements G11C17/14 takes precedence
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 2213/77 Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used
• CPC Class Codes: G11C 29/00 Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 7/00 Arrangements for writing information into, or reading information out from, a digital store G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413
• CPC Class Codes: H01L 21/82 to produce devices, e.g. integrated circuits, each consisting of a plurality of components
• CPC Class Codes: H01L 29/0676 oriented perpendicular or at an angle to a substrate
• CPC Class Codes: H10B 63/00 Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
• CPC Class Codes: H10N 70/00 Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching integrated devices or assemblies of multiple devices H10N79/00

Abstract

A method of making a nonvolatile memory device includes forming a first electrode, forming at least one nonvolatile memory cell comprising a first diode portion, a second diode portion and an antifuse separating the first diode portion from the second diode portion, and forming a second electrode over the at least one nonvolatile memory cell.

Claims

1. A method of making a nonvolatile memory device, comprising:

forming a first electrode;

forming at least one nonvolatile memory cell comprising a first diode portion, a second diode portion and an antifuse separating the first diode portion from the second diode portion; and

forming a second electrode over the at least one nonvolatile memory cell.

2. The method of claim 1, wherein:

the first diode portion comprises a p-type semiconductor region and the second diode portion comprises an n-type semiconductor region; and

the antifuse comprises an antifuse dielectric layer located between the p-type semiconductor region and the n-type semiconductor region.

3. The method of claim 1, further comprising forming an intrinsic semiconductor region adjacent to the antifuse dielectric layer between the p-type semiconductor region and the n-type semiconductor region.

4. The method of claim 3, wherein:

the diode comprises a polycrystalline silicon, germanium or silicon-germanium p-i-n pillar diode having a substantially cylindrical shape; and

the antifuse dielectric layer comprises a silicon oxide, silicon nitride or metal oxide layer.

5. The method of claim 3, wherein the p-type semiconductor region is located below the antifuse dielectric layer and the n-type semiconductor region is located above the antifuse dielectric layer.

6. The method of claim 3, wherein the n-type semiconductor region is located below the antifuse dielectric layer and the p-type semiconductor region is located above the antifuse dielectric layer.

7. The method of claim 3, wherein the intrinsic semiconductor region is located below the antifuse dielectric layer.

8. The method of claim 3, wherein the intrinsic semiconductor region is located above the antifuse dielectric layer.

9. The method of claim 3, wherein:

the n-type semiconductor region is located below the antifuse dielectric layer and the intrinsic semiconductor region is located on the antifuse dielectric layer; and

the p-type semiconductor region is formed by ion implanting p-type dopant ions into an upper portion of the intrinsic semiconductor region.

10. The method of claim 3, further comprising patterning the first diode portion, the second diode portion and the antifuse dielectric layer such that the first diode portion, the second diode portion and the metal oxide antifuse dielectric layer form a pillar having a substantially cylindrical shape.

11. The method of claim 3, further comprising applying a forward bias to the nonvolatile memory cell to rupture the antifuse dielectric layer such that a conductive link extends through the antifuse dielectric layer and such that the first diode portion and the second diode portion form a diode, and to switch the diode from the first resistivity, unprogrammed state to the second resistivity, programmed state, wherein the second resistivity state is lower than the first resistivity state.

12. The method of claim 11, further comprising applying a reverse bias to the diode to switch the diode to a third resistivity, unprogrammed state, wherein the third resistivity state is higher than the second resistivity state.

13. A method of operating a nonvolatile memory device, comprising:

providing at least one nonvolatile memory cell which comprises a first diode portion, a second diode portion and an antifuse dielectric layer separating the first diode portion from the second diode portion; and

applying a forward bias to the nonvolatile memory cell to rupture the antifuse dielectric layer such that a conductive link extends through the antifuse dielectric layer and such that the first diode portion and the second diode portion form a diode, and to switch the diode from the first resistivity, unprogrammed state to the second resistivity, programmed state, wherein the second resistivity state is lower than the first resistivity state.

14. The method of claim 13, further comprising applying a reverse bias to the diode to switch the diode to a third resistivity, unprogrammed state, wherein the third resistivity state is higher than the second resistivity state.

15. The method of claim 14, further comprising:

applying a forward bias to the diode to switch the diode to a fourth resistivity, programmed state, wherein the fourth resistivity state is lower than the third resistivity state; and

sensing a resistivity state of the diode as a data state of the memory cell.

16. The method of claim 13, wherein:

the first diode portion comprises a p-type semiconductor region and the second diode portion comprises an n-type semiconductor region;

the antifuse comprises an antifuse dielectric layer located between the p-type semiconductor region and the n-type semiconductor region; and

an intrinsic semiconductor region is located adjacent to the antifuse dielectric layer between the p-type semiconductor region and the n-type semiconductor region.

17. A method of operating a nonvolatile memory device, comprising:

providing at least one nonvolatile memory cell which comprises a first diode portion, a second diode portion and an antifuse dielectric layer separating the first diode portion from the second diode portion, wherein a conductive link extends through the antifuse dielectric layer such that the first diode portion and the second diode portion form a diode, and the diode has been switched from the first resistivity, unprogrammed state to the second resistivity, programmed state, wherein the second resistivity state is lower than the first resistivity state; and

applying a reverse bias to the diode to switch the diode to a third resistivity, unprogrammed state, wherein the third resistivity state is higher than the second resistivity state.

18. The method of claim 17, further comprising:

applying a forward bias to the diode to switch the diode to a fourth resistivity, programmed state, wherein the fourth resistivity state is lower than the third resistivity state; and

sensing a resistivity state of the diode as a data state of the memory cell.

19. The method of claim 17, wherein:

the first diode portion comprises a p-type semiconductor region and the second diode portion comprises an n-type semiconductor region;

the antifuse comprises an antifuse dielectric layer located between the p-type semiconductor region and the n-type semiconductor region; and

an intrinsic semiconductor region is located adjacent to the antifuse dielectric layer between the p-type semiconductor region and the n-type semiconductor region.

20. The method of claim 17, wherein:

the diode is switched into the second, programmed state in a factory in which the memory cell is fabricated; and

the step of applying the reverse bias is performed by a user of the memory cell after the memory cell leaves the factory in which the memory cell is fabricated.