METHOD AND APPARATUS FOR READING DATA FROM NONVOLATILE MEMORY
First Claim
1. A method for reading memory cells in a plurality of electrically adjacent memory cells all sharing a word line in a memory array, the plurality of cells including a first cell and a last cell, each of the cells in the plurality sharing a bit line with each of its adjacent cells, the first and last cells being further connected to first and last bit lines, respectively, which are not shared with any other cells in the plurality,the bit lines including a first group of at least one adjacent bit line and a last group of at least one adjacent bit line distinct from the first group, the first group being adjacent to the first bit line and the last group being adjacent to the last bit line,the bit line in the first group that is shared with the first cell in the plurality being a first common bit line, and the bit line in the last group that is shared with the last cell in the plurality being a last common bit line,the method comprising the steps of:
- precharging both the first and last common bit lines to respective precharged states; and
while both the first and last common bit lines are in their respective precharged states, initiating a sense operation to read both the first and last cells substantially simultaneously.
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Accused Products
Abstract
Roughly described, a memory includes first and second target memory cells in a plurality of electrically adjacent memory cells all sharing a word line. The two target memory cells are separated from each other by at least one additional memory cell, and first current path terminals of the target memory cells bracket second current path terminals of the target memory cells electrically along the word line. The two target memory cells are read by connecting the first current path terminals of the two target memory cells to ground, precharging the second current path terminals of the two target memory cells to respective precharged states, and while both second current path terminals are in their respective precharged states, initiating a sense operation to read both the first and second target memory cells substantially simultaneously.
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Citations
15 Claims
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1. A method for reading memory cells in a plurality of electrically adjacent memory cells all sharing a word line in a memory array, the plurality of cells including a first cell and a last cell, each of the cells in the plurality sharing a bit line with each of its adjacent cells, the first and last cells being further connected to first and last bit lines, respectively, which are not shared with any other cells in the plurality,
the bit lines including a first group of at least one adjacent bit line and a last group of at least one adjacent bit line distinct from the first group, the first group being adjacent to the first bit line and the last group being adjacent to the last bit line, the bit line in the first group that is shared with the first cell in the plurality being a first common bit line, and the bit line in the last group that is shared with the last cell in the plurality being a last common bit line, the method comprising the steps of: -
precharging both the first and last common bit lines to respective precharged states; and while both the first and last common bit lines are in their respective precharged states, initiating a sense operation to read both the first and last cells substantially simultaneously. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A memory system comprising:
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a plurality of electrically adjacent memory cells all sharing a word line in a memory array, the plurality of cells including a first cell and a last cell, each of the cells in the plurality sharing a bit line with each of its adjacent cells, the first and last cells being further connected to first and last bit lines, respectively, which are not shared with any other cells in the plurality, the bit lines including a first group of at least one adjacent bit line and a last group of at least one adjacent bit line distinct from the first group, the first group being adjacent to the first bit line and the last group being adjacent to the last bit line, the bit line in the first group that is shared with the first cell in the plurality being a first common bit line, and the bit line in the last group that is shared with the last cell in the plurality being a last common bit line; means for precharging both the first and last common bit lines to respective precharged states; and means for initiating a sense operation to read both the first and last cells substantially simultaneously, the sense operation being initiated while both the first and last common bit lines are in their respective precharged states.
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9. A memory system including a control unit for reading memory cells in a plurality of electrically adjacent memory cells all sharing a word line in a memory array, the plurality of cells including a first cell and a last cell, each of the cells in the plurality sharing a bit line with each of its adjacent cells, the first and last cells being further connected to first and last bit lines, respectively, which are not shared with any other cells in the plurality,
the bit lines including a first group of at least one adjacent bit line and a last group of at least one adjacent bit line distinct from the first group, the first group being adjacent to the first bit line and the last group being adjacent to the last bit line, the bit line in the first group that is shared with the first cell in the plurality being a first common bit line, and the bit line in the last group that is shared with the last cell in the plurality being a last common bit line, wherein the control unit generates control signals which cause: -
both the first and last common bit lines to be precharged to respective precharged states; and while both the first and last common bit lines are in their respective precharged states, a sense operation to be initiated to read both the first and last cells substantially simultaneously.
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10. A method for reading first and second target memory cells in a plurality of electrically adjacent memory cells all sharing a word line in a memory array, the first and second target memory cells each having respective first and second current path terminals, the second current path terminals of the first and second target memory cells being separated from each other electrically along the word line by at least one additional memory cell, and the first current path terminals of the first and second target memory cells bracketing the second current path terminals of the first and second target memory cells electrically along the word line, comprising the steps of:
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connecting the first current path terminal of the first target memory cell through selection circuitry to ground; connecting the second current path terminal of the first target memory cell through selection circuitry to a first sensing node; connecting the first current path terminal of the second target memory cell through selection circuitry to ground; connecting the second current path terminal of the second target memory cell through selection circuitry to a second sensing node; precharging both the first and second sensing nodes to respective precharged states; and while both the first and second sensing nodes are in their respective precharged states, initiating a sense operation to read both the first and second target memory cells substantially simultaneously. - View Dependent Claims (11)
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12. A memory system comprising:
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a plurality of electrically adjacent memory cells all sharing a word line in a memory array, the plurality of memory cells including first and second target memory cells, the first and second target memory cells each having respective first and second current path terminals, the second current path terminals of the first and second target memory cells being separated from each other electrically along the word line by at least one additional memory cell, and the first current path terminals of the first and second target memory cells bracketing the second current path terminals of the first and second target memory cells electrically along the word line; means for connecting the first current path terminal of the first target memory cell to ground; means for connecting the second current path terminal of the first target memory cell to a first sensing node; means for connecting the first current path terminal of the second target memory cell to ground; means for connecting the second current path terminal of the second target memory cell to a second sensing node; means for precharging both the first and second sensing nodes to respective precharged states; and means for initiating a sense operation to read both the first and second target memory cells substantially simultaneously, the sense operation being initiated while both the first and second sensing nodes are in their respective precharged states.
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13. A memory system including a control unit for reading first and second target memory cells in a plurality of electrically adjacent memory cells all sharing a word line in a memory array, the first and second target memory cells each having respective first and second current path terminals, the second current path terminals of the first and second target memory cells being separated from each other electrically along the word line by at least one additional memory cell, and the first current path terminals of the first and second target memory cells bracketing the second current path terminals of the first and second target memory cells electrically along the word line, wherein the control unit generates control signals which cause:
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the first current path terminal of the first target memory cell to be connected through selection circuitry to ground; the second current path terminal of the first target memory cell to be connected through selection circuitry to a first sensing node; the first current path terminal of the second target memory cell to be connected through selection circuitry to ground; the second current path terminal of the second target memory cell to be connected through selection circuitry to a second sensing node; both the first and second sensing nodes to be precharged to respective precharged states; and while both the first and second sensing nodes are in their respective precharged states, a sense operation to be initiated to read both the first and second target memory cells substantially simultaneously. - View Dependent Claims (14, 15)
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Specification