Current sensing for flash

• US 20080013382A1
• Filed: 07/14/2006
• Published: 01/17/2008
• Est. Priority Date: 07/14/2006
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Tang, Qiang
• Granted Patent: US 7,688,635 B2
• Time in Patent Office: Days
• US Class Current: 365/185.24
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells

Abstract

A current sensing data read/verify process and sense amplifier is described that senses memory cells of a non-volatile memory array utilizing a current sensing process that places a current source to provide current to the bit line. The voltage level of the bit line is then set by the current provided by the current source and the current sunk from the bit line through the selected memory cell to the source line, which is dependent on the threshold voltage of its programmed or erased state. If the selected memory cell is erased, current flows through the memory cell to the source line and the bit line voltage falls. If the selected memory cell is programmed, little or no current flows through the cell, and the bit line voltage rises and is sensed by the sense amplifier.

Claims

1. A method of sensing a threshold voltage of a non-volatile memory cell, comprising:

placing a read voltage on a control gate of a selected non-volatile memory cell;

coupling the non-volatile memory cell to a source line and a bit line;

providing a current from a current source to the bit line coupled to the non-volatile memory cell; and

sensing the voltage level of the bit line to determine the threshold voltage level of the selected non-volatile memory cell.

2. The method of claim 1, wherein providing a current from a current source to the bit line coupled to the non-volatile memory cell further comprises providing a current from a current limited current source to the bit line coupled to the non-volatile memory cell.

3. The method of claim 1, wherein providing a current from a current source to the bit line coupled to the non-volatile memory cell further comprises providing a current from a current source having a high internal resistance to the bit line coupled to the non-volatile memory cell.

4. The method of claim 1, wherein providing a current from a current source to the bit line coupled to the non-volatile memory cell further comprises providing a current from a current source limited by a saturation current of an internal device to the bit line coupled to the non-volatile memory cell.

5. The method of claim 1, further comprising turning off the current source after sensing the voltage level of the bit line.

6. The method of claim 1, wherein sensing the voltage level of the bit line to determine the threshold voltage level of the selected non-volatile memory cell further comprises sensing the voltage level of the bit line by amplifying a voltage level change of the bit line by restricting current flow to the non-volatile memory cell from a first portion of the bit line as the voltage level of the bit line increases.

7. The method of claim 6, wherein amplifying a voltage level change of the bit line by restricting current flow to the non-volatile memory cell from a first portion of the bit line as the voltage level of the bit line increases further comprises isolating a second portion of the bit line coupled to the non-volatile memory cell from the current source as the voltage level increases.

8. The method of claim 1, wherein the current source either sources a current to the bit line or sinks a current from the bit line.

9. The method of claim 1, wherein the method is one of a read operation and a verify operation.

10. The method of claim 1, wherein the non-volatile memory cell is a multi-level cell (MLC).

11. The method of claim 1, wherein the non-volatile memory cell is in a NAND memory cell string.

12. The method of claim 1, further comprising precharging the bit line to a selected voltage level before coupling the non-volatile memory cell to the bit line.

13. A method of sensing a data value in a memory cell of a non-volatile NAND architecture memory string, comprising:

applying a read voltage to a selected word line coupled to a selected non-volatile memory cell of the NAND architecture memory string that is selected for reading;

applying a pass voltage to one or more unselected word lines and coupled non-volatile memory cells of the non-volatile NAND architecture memory string;

coupling the non-volatile NAND architecture memory string to a source line and a bit line;

sourcing current from a current limited current source on to the bit line; and

sensing the voltage of the bit line to determine the data value stored in the selected non-volatile memory cell of the non-volatile NAND architecture memory string.

14. The method of claim 13, wherein sourcing current from a current limited current source on to the bit line further comprises sourcing current from a current source having a high internal resistance to the bit line coupled to the non-volatile memory cell.

15. The method of claim 13, wherein sourcing current from a current limited current source to the bit line coupled to the non-volatile memory cell further comprises sourcing current from a current source limited by a saturation current of a transistor to the bit line coupled to the non-volatile memory cell.

16. The method of claim 13, further comprising turning off the current limited current source after sensing the voltage of the bit line.

17. The method of claim 13, wherein sensing the voltage of the bit line to determine the data value stored in the selected non-volatile memory cell of the non-volatile NAND architecture memory string further comprises sensing the voltage of the bit line by amplifying a voltage change of the bit line by restricting current flow to the non-volatile NAND architecture memory string as the voltage of the bit line increases.

18. The method of claim 13, wherein amplifying a voltage change of the bit line by restricting current flow to the non-volatile NAND architecture memory string as the voltage of the bit line increases further comprises amplifying a voltage change by isolating the bit line from the current source as the voltage increases.

19. The method of claim 13, wherein sourcing current from a current limited current source on to the bit line further comprises sinking a current from the bit line through the current limited current source.

20. The method of claim 13, wherein the non-volatile memory cells of the non-volatile NAND architecture memory string are multi-level cells (MLCs).

21. The method of claim 13, further comprising precharging the bit line to a selected voltage before coupling the non-volatile NAND architecture memory string to the bit line.

22. A method of operating a non-volatile memory device, comprising:

applying a read voltage to one or more word lines coupled to one or more selected non-volatile memory cells of a memory array of the non-volatile memory device;

coupling each of the one or more selected non-volatile memory cells to a source line;

coupling each of the one or more selected non-volatile memory cells to a bit line of one or more bit lines;

sourcing current from a current limited current source on to each bit line of the one or more bit lines; and

sensing the voltage level of each bit line of the one or more bit lines to determine a data value.

23. The method of claim 22, wherein sourcing current from a current limited current source on to each bit line of the one or more bit lines further comprises sourcing current from a current limited current source having one of a high internal resistance and a limited saturation current.

24. The method of claim 22, wherein the non-volatile memory device is a NAND architecture non-volatile memory device.

25. The method of claim 22, further comprising turning off the current limited current source after sensing the voltage level of each bit line.

26. The method of claim 22, wherein sensing the voltage level of each bit line of the one or more bit lines to determine a data value further comprises amplifying a voltage level change of a first portion of each bit line of the one or more bit lines by restricting current flow to a second portion of each bit line coupled to the selected non-volatile memory cell as the voltage level of the bit line increases.

27. The method of claim 22, wherein the plurality of non-volatile memory cells are multi-level cells (MLCs).

28. The method of claim 22, further comprising precharging each bit line of the one or more bit lines to a selected voltage.

29. A method of operating sense amplifier, comprising:

sourcing current from a current limited current source on to a coupled bit line; and

sensing the voltage potential of the bit line to determine the data value stored in a non-volatile memory cell coupled to the bit line.

30. The method of claim 29, wherein sourcing current from a current limited current source on to a coupled bit line further comprises sourcing current from a current limited current source having one of a high internal resistance and a limited saturation current.

31. The method of claim 29, further comprising turning off the current source after sensing a final voltage potential of the bit line.

32. The method of claim 29, wherein sensing the voltage potential of the bit line to determine the data value stored in a non-volatile memory cell coupled to the bit line further comprises amplifying a change in voltage potential of an internal circuit node of the sense amplifier that is coupled to both the current limited current source and the bit line by restricting current flow from the internal node to the bit line as the voltage potential of the internal node increases.

33. The method of claim 29, wherein the current limited current source sinks a current from the bit line.

34. The method of claim 29, wherein the non-volatile memory cell is a multi-level cell (MLC).

35. A sense amplifier, comprising:

a current limited current source, wherein the current limited current source is coupled to a bit line connection of the sense amplifier;

a sensing transistor having a control gate coupled to the bit line connection and a first source/drain region coupled to a ground; and

a data latch coupled to a second source/drain region of the sensing transistor.

36. The sense amplifier of claim 35, wherein the current limited current source is a current limited current source having one of a high internal resistance and a limited saturation current.

37. The sense amplifier of claim 35, wherein the current limited current source is one of a PFET transistor, a NFET transistor, a long channel PFET transistor, a long channel NFET transistor, a diode coupled transistor, a resistor, and a current mirror.

38. The sense amplifier of claim 35, wherein the current limited current source is adapted to provide one of a selected current sunk from the bit line connection and a selected current sourced to the bit line connection.

39. The sense amplifier of claim 35, wherein the sensing transistor is a long channel transistor, where the long channel transistor has a channel length greater than one and a half times the channel length of a conventional transistor of a semiconductor manufacturing process.

40. The sense amplifier of claim 35, wherein the sensing transistor is one of a PFET transistor and a NFET transistor.

41. The sense amplifier of claim 35, wherein the first source/drain region of the sensing transistor is coupled to a power rail.

42. The sense amplifier of claim 35, further comprising an isolation transistor coupled between the bit line connection and a node formed by the current limited current source and the control gate of the sensing transistor, wherein the isolation transistor is adapted to isolate the bit line connection from the node after a data value is sensed from the bit line connection.

43. The sense amplifier of claim 42, wherein the isolation transistor is a NFET transistor and has a control gate coupled to an output of the data latch.

44. The sense amplifier of claim 35, further comprising a first transistor coupled between the bit line connection and a node formed by the current limited current source and the control gate of the sensing transistor, wherein a control gate of the first transistor is coupled to a first voltage.

45. The sense amplifier of claim 44, wherein the first transistor is a long channel NFET transistor, where the long channel transistor has a channel length greater than one and a half times the channel length of an average feature sized transistor of a semiconductor manufacturing process.

46. The sense amplifier of claim 35, wherein the data latch is adapted to be reset before sensing a data value on the bit line connection.

47. The sense amplifier of claim 35, wherein the data latch is one of a pair of feedback coupled inverters and a cross coupled pair of NAND gates.

48. A non-volatile memory device, comprising:

a non-volatile memory array having a plurality of non-volatile memory cells, wherein each non-volatile memory cell has a control gate coupled to a word line, a first and second source/drain regions that are selectively coupleable to a bit line and a source line; and

a plurality of sense amplifiers, wherein each sense amplifier of the plurality of sense amplifiers is selectively coupled to one or more associated bit lines and comprises,

a current limited current source, wherein the current limited current source is adapted to source current on to a selected bit line coupled to the sense amplifier,

a sensing transistor having a control gate coupled to the selected associated bit line and a source region coupled to a ground, and

a data latch coupled to a drain region of the sensing transistor.

49. The non-volatile memory device of claim 48, wherein the current limited current source is a current limited current source having one of a high internal resistance and a limited saturation current.

50. The non-volatile memory device of claim 48, further comprising a plurality of multiplexers, wherein a multiplexer of the plurality of multiplexers is coupled between each sense amplifier and the one or more associated bit lines.

51. The non-volatile memory device of claim 48, wherein the non-volatile memory array is one of a NAND architecture memory array and a NOR architecture memory array.

52. The non-volatile memory device of claim 48, wherein the current limited current source of each sense amplifier is one of a PFET transistor, a NFET transistor, a long channel PFET transistor, a long channel NFET transistor, a diode coupled transistor, a resistor, and a current mirror.

53. The non-volatile memory device of claim 48, wherein the sensing transistor of each sense amplifier is a long channel transistor, where the long channel transistor has a channel length greater than one and a half times the channel length of a conventional transistor of a semiconductor manufacturing process.

54. The non-volatile memory device of claim 48, wherein each sense amplifier further comprises an isolation transistor coupled between the selected associated bit line and a node formed by the current limited current source and the control gate of the sensing transistor, where the isolation transistor is adapted to isolate the selected associated bit line from the node after a data value is sensed from the bit line connection.

55. The non-volatile memory device of claim 54, wherein the isolation transistor is a NFET transistor and has a control gate coupled to an output of the data latch.

56. The non-volatile memory device of claim 48, further comprising a first transistor coupled between the selected associated bit line and a node formed by the current limited current source and the control gate of the sensing transistor, wherein a control gate of the first transistor is coupled to a first voltage.

57. The non-volatile memory device of claim 56, wherein the first transistor is a long channel NFET transistor, where the long channel transistor has a channel length greater than one and a half times the channel length of a conventional transistor of a semiconductor manufacturing process.

58. The non-volatile memory device of claim 48, wherein the data latch is adapted to be reset before sensing a data value on the bit line connection.

59. A non-volatile NAND architecture memory device, comprising:

a NAND architecture non-volatile memory array having a plurality of memory blocks;

a sense amplifier circuit coupled to the array; and

a control circuit, wherein the control circuit is adapted to read memory cells in a selected memory block of the non-volatile memory array by,

applying a read voltage to a selected word line coupled to a selected non-volatile memory cell of a NAND architecture memory string that is selected for reading,

applying a pass voltage to one or more unselected word lines and coupled non-volatile memory cells of the non-volatile NAND architecture memory string,

coupling the non-volatile NAND architecture memory string to a source line and a bit line,

coupling the sense amplifier circuit to the bit line,

sourcing current from a current limited current source on to the bit line, and

sensing the voltage of the bit line to determine the data value stored in the selected non-volatile memory cell of the non-volatile NAND architecture memory string.

60. The non-volatile NAND architecture memory device of claim 59, wherein the current limited current source is a current limited current source having one of a high internal resistance and a limited saturation current.

61. The non-volatile NAND architecture memory device of claim 59, wherein the current source of the sense amplifier circuit is one of a PFET transistor, a NFET transistor, a long channel PFET transistor, a long channel NFET transistor, a diode coupled transistor, a resistor, and a current mirror.

62. The non-volatile NAND architecture memory device of claim 59, wherein each sense amplifier circuit farther comprises an isolation transistor coupled between the bit line and the current limited current source, where the isolation transistor is adapted to isolate the bit line from the current limited current source after a data value is sensed from the bit line.

63. The non-volatile NAND architecture memory device of claim 62, wherein the isolation transistor is a NFET transistor and has a control gate coupled to an output of the sense amplifier circuit.

64. The non-volatile NAND architecture memory device of claim 59, further comprising a first transistor coupled between the bit line and the current limited current source, wherein the first transistor is adapted to amplify a rising voltage level of the bit line.

65. The non-volatile NAND architecture memory device of claim 64, wherein the first transistor is a long channel NFET transistor, where the long channel transistor has a channel length greater than one and a half times the channel length of a conventional transistor of a semiconductor manufacturing process.

66. A system, comprising:

a host coupled to a non-volatile memory device, the non-volatile memory device comprising,

a non-volatile memory array having a plurality of non-volatile memory cells, wherein each non-volatile memory cell has a control gate coupled to a word line, a first and second source/drain regions that are selectively coupleable to a bit line and a source line; and

a plurality of sense amplifiers, wherein each sense amplifier of the plurality of sense amplifiers is selectively coupled to one or more bit lines and comprises,

a current limited current source, wherein the current limited current source is adapted to source current on to a selected bit line coupled to the sense amplifier,

a sensing transistor having a control gate coupled to the selected bit line and a source region coupled to a ground, and

a data latch coupled to a drain region of the sensing transistor.

67. The system of claim 66, wherein the host is one of a processor and a memory controller.

68. The system of claim 66, wherein the current limited current source is a current limited current source having one of a high internal resistance and a limited saturation current.

69. The system of claim 66, wherein the non-volatile memory array is one of a NAND architecture memory array and a NOR architecture memory array.

70. The system of claim 66, wherein each sense amplifier further comprises an isolation transistor coupled between the selected bit line and a node formed by the current limited current source and the control gate of the sensing transistor, where the isolation transistor is adapted to isolate the selected bit line from the node after a data value is sensed from the bit line connection.

71. The system of claim 66, further comprising a first transistor coupled between the selected bit line and a node formed by the current limited current source and the control gate of the sensing transistor, wherein a control gate of the first transistor is coupled to a first voltage.

72. A memory module, comprising:

a plurality of contacts; and

two or more memory devices, each having access lines selectively coupled to the plurality of contacts;

wherein at least one of the memory device comprises;

a NAND architecture non-volatile memory array having a plurality of memory blocks,

wherein the memory module is adapted to read memory cells in a selected block of the non-volatile memory array by,

applying a read voltage to a selected word line coupled to a selected non-volatile memory cell of a NAND architecture memory string that is selected for reading,

applying a pass voltage to one or more unselected word lines and coupled non-volatile memory cells of the non-volatile NAND architecture memory string,

coupling the non-volatile NAND architecture memory string to a source line and a bit line,

sourcing current from a current limited current source on to the bit line, and

sensing the voltage of the bit line to determine the data value stored in the selected non-volatile memory cell of the non-volatile NAND architecture memory string.

73. The memory module of claim 72, further comprising a memory controller coupled to the one or more memory devices for controlling operation of each memory device in response to the host system.

74. A memory module, comprising:

a housing having a plurality of contacts; and

one or more memory devices enclosed in the housing and selectively coupled to the plurality of contacts;

wherein the memory module is adapted to read memory cells in a selected block of at least one of the memory devices by,

applying a read voltage to a word line coupled to a selected non-volatile memory cell of a non-volatile memory array of the at least one memory device;

coupling the selected non-volatile memory cell to a source line and a bit line;

sourcing current from a current limited current source on to the bit line; and

sensing the voltage level of the bit line to determine the data value stored in the selected non-volatile memory cell of the non-volatile memory array.