Isolation regions

• US 20080014710A1
• Filed: 07/14/2006
• Published: 01/17/2008
• Est. Priority Date: 07/14/2006
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Fang, Xiaolong, Bian, Zailong
• Granted Patent: US 7,968,425 B2
• Time in Patent Office: Days
• US Class Current: 438/424
• CPC Class Codes: H01L 21/76232 of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls H01L21/76229 takes precedence
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

Methods and apparatus are provided. An isolation region is formed by lining a trench formed in a substrate with a first dielectric layer by forming the first dielectric layer adjoining exposed substrate surfaces within the trench using a high-density plasma process, forming a layer of spin-on dielectric material on the first dielectric layer so as to fill a remaining portion of the trench, and densifying the layer of spin-on dielectric material.

Claims

1. A method of forming an isolation region in a substrate, comprising:

lining a trench formed in the substrate with a first dielectric layer by forming the first dielectric layer adjoining exposed substrate surfaces within the trench using a high-density plasma process;

forming a layer of spin-on dielectric material on the first dielectric layer so as to fill a remaining portion of the trench; and

densifying the layer of spin-on dielectric material.

2. The method of claim 1, wherein densifying the layer of spin-on dielectric material comprises first and second densifications.

3. The method of claim 1, wherein the first dielectric layer is a high-density plasma oxide.

4. The method of claim 1, wherein densifying the layer of spin-on dielectric material causes the first dielectric layer and the layer of spin-on dielectric material to have substantially similar chemical compositions.

5. The method of claim 1, wherein densifying the layer of spin-on dielectric material causes the first dielectric layer and a portion of the layer of spin-on dielectric material to have substantially the same etch rates.

6. The method of claim 1, wherein densifying the layer of spin-on dielectric material comprises steam densification or steam oxidation and annealing.

7. A method of forming an isolation region in a substrate, comprising:

lining a trench formed in the substrate with a layer of high-density plasma oxide by forming the layer of high-density plasma oxide adjoining exposed substrate surfaces within the trench;

forming a layer of spin-on dielectric material on the layer of high-density plasma oxide so as to fill a remaining portion of the trench;

oxidizing the layer of spin-on dielectric material; and

annealing the oxidized layer of spin-on dielectric material.

8. The method of claim 7, wherein oxidizing the layer of spin-on dielectric material comprises steam oxidation.

9. A method of forming an isolation region in a semiconductor substrate, comprising:

forming a trench through a first dielectric layer formed on the substrate, through a second dielectric layer formed on the first dielectric layer and into the substrate;

lining an interior of the trench with a third dielectric layer;

forming a fourth dielectric layer overlying the first, second, and third dielectric layers such that the fourth dielectric layer overfills the trench;

densifying the fourth dielectric layer using a first densification process;

removing a portion of the densified fourth dielectric layer to expose an upper surface of the second dielectric layer;

removing the second dielectric layer to expose an upper surface of the first dielectric layer so that portions of the third dielectric layer and densified fourth dielectric layer extend above the upper surface of the first dielectric layer; and

further densifying at least the portion of the densified fourth dielectric layer extending above the upper surface of the first dielectric layer using a second densification process.

10. The method of claim 9, wherein lining an interior of the trench with a third dielectric layer comprises a high-density plasma process.

11. The method of claim 9, wherein the third dielectric layer is a high-density plasma oxide or TEOS.

12. The method of claim 9, wherein the fourth dielectric layer is a layer of spin-on dielectric material.

13. The method of claim 9, wherein the first densification process is a steam-oxidation process.

14. The method of claim 13, wherein the second densification process is an annealing process.

15. The method of claim 9 further comprises removing the first dielectric layer after the second densification process to expose portions of the substrate.

16. The method of claim 9, wherein the first dielectric layer is a pad oxide layer.

17. The method of claim 9, wherein the second dielectric layer is a nitride layer.

18. The method of claim 9, wherein removing the second dielectric layer comprises a dry etch.

19. A method of forming an isolation region in a semiconductor substrate, comprising:

forming a trench through a first dielectric layer formed on the substrate, through a second dielectric layer formed on the first dielectric layer and into the substrate;

lining an interior of the trench with a layer of high-density plasma oxide, wherein the layer of high-density plasma oxide adjoins exposed portions of the first and second dielectric layers within the trench and exposed portions of the substrate within the trench;

forming a layer of spin-on dielectric material overlying the first and second dielectric layers and the layer of high-density plasma oxide such that the layer of spin-on dielectric material overfills the trench;

oxidizing the layer of spin-on dielectric material;

removing a portion of the oxidized layer of spin-on dielectric material to expose an upper surface of the second dielectric layer;

removing the second dielectric layer to expose an upper surface of the first dielectric layer so that portions of the layer of high-density plasma oxide material and the oxidized layer of spin-on dielectric material extend above the upper surface of the first dielectric layer; and

annealing at least the oxidized portion of the layer of spin-on dielectric material extending above the upper surface of the first dielectric layer.

20. The method of claim 19, wherein oxidizing the layer of spin-on dielectric material comprises steam-oxidizing the layer of spin-on dielectric material.

21. The method of claim 19 further comprises removing the first dielectric layer after annealing at least the oxidized portion of the layer of spin-on dielectric material to expose portions of the substrate.

22. A method of forming a portion of an integrated circuit device contained on a semiconductor substrate, the method comprising:

forming one or more isolation regions in the substrate, comprising;

forming a trench through a first dielectric layer formed on the substrate, through a second dielectric layer formed on the first dielectric layer and into the substrate;

lining an interior of the trench with a third dielectric layer;

forming a fourth dielectric layer overlying the first, second, and third dielectric layers such that the fourth dielectric layer overfills the trench;

densifying the fourth dielectric layer using a first densification process;

removing a portion of the densified fourth dielectric layer to expose an upper surface of the second dielectric layer;

removing the second dielectric layer to expose an upper surface of the first dielectric layer so that portions of the third and densified fourth dielectric layers extend above the upper surface of the first dielectric layer; and

further densifying at least the portion of the densified fourth dielectric layer extending above the upper surface of the first dielectric layer using a second densification process; and

removing the first dielectric layer after the second densification process to expose portions of the substrate on either side of each of the one or more isolation regions for defining active regions on the substrate on either side of the one or more isolation regions on which integrated circuit components will be formed.

23. The method of claim 22, wherein lining an interior of the trench with a third dielectric layer comprises a high-density plasma process.

24. The method of claim 22, wherein the third dielectric layer is a high-density plasma oxide or TEOS.

25. The method of claim 22, wherein the fourth dielectric layer is a layer of spin-on dielectric material.

26. The method of claim 22, wherein the first densification process is a steam-oxidation process.

27. The method of claim 26, wherein the second densification process is an annealing process.

28. A method of forming a portion of an integrated circuit device contained on a semiconductor substrate, the method comprising:

forming one or more isolation regions in the substrate, comprising;

forming a trench through a first dielectric layer formed on the substrate, through a second dielectric layer formed on the first dielectric layer and into the substrate;

lining an interior of the trench with a layer of high-density plasma oxide, wherein the layer of high-density plasma oxide adjoins exposed portions of the first and second dielectric layers within the trench and exposed portions of the substrate within the trench;

forming a layer of spin-on dielectric material overlying the first and second dielectric layers and the layer of high-density plasma oxide such that the layer of spin-on dielectric material overfills the trench;

oxidizing the layer of spin-on dielectric material;

removing a portion of the oxidized layer of spin-on dielectric material to expose an upper surface of the second dielectric layer;

removing the second dielectric layer to expose an upper surface of the first dielectric layer so that portions of the layer of high-density plasma oxide material and the oxidized layer of spin-on dielectric material extend above the upper surface of the first dielectric layer; and

annealing at least the oxidized portion of the layer of spin-on dielectric material extending above the upper surface of the first dielectric layer; and

removing the first dielectric layer after annealing at least the oxidized portion of the layer of spin-on dielectric material extending above the upper surface of the first dielectric layer to expose portions of the substrate on either side of each of the one or more isolation regions for defining active regions on the substrate on either side of each of the one or more isolation regions on which integrated circuit components will be formed.

29. A method of forming a portion of a memory array, the method comprising:

forming one or more isolation regions in a substrate, comprising;

forming a trench through a first dielectric layer formed on the substrate, through a second dielectric layer formed on the first dielectric layer and into the substrate;

lining an interior of the trench with a third dielectric layer;

forming a fourth dielectric layer overlying the first, second, and third dielectric layers such that the fourth dielectric layer overfills the trench;

densifying the fourth dielectric layer using a first densification process;

removing a portion of the densified fourth dielectric layer to expose an upper surface of the second dielectric layer;

removing the second dielectric layer to expose an upper surface of the first dielectric layer so that portions of the third and densified fourth dielectric layers extend above the upper surface of the first dielectric layer; and

further densifying at least the portion of the densified fourth dielectric layer extending above the upper surface of the first dielectric layer using a second densification process;

removing the first dielectric layer after the second densification process to expose portions of the substrate on either side of each of the one or more isolation regions;

forming a fifth dielectric layer on the exposed portions of the substrate on either side of each of the one or more isolation regions;

forming a first conductive layer overlying the fifth dielectric layer;

forming a sixth dielectric layer overlying the first conductive layer and each of the one or more isolation regions; and

forming a second conductive layer overlying the sixth dielectric layer.

30. The method of claim 29, wherein lining an interior of the trench with a third dielectric layer comprises a high-density plasma process.

31. The method of claim 29, wherein the third dielectric layer is a high-density plasma oxide or TEOS.

32. The method of claim 29, wherein the fourth dielectric layer is a layer of spin-on dielectric material.

33. The method of claim 29, wherein the first densification process is a steam-oxidation process.

34. The method of claim 33, wherein the second densification process is an annealing process.

35. The method of claim 29, wherein the first dielectric layer is a pad oxide layer.

36. The method of claim 29, wherein the second dielectric layer is a nitride layer.

37. The method of claim 29, wherein removing the second dielectric layer comprises a dry etch.

38. The method of claim 29, wherein the second conductive layer is selected from the group consisting of refractory metals, refractory metal silicides, and a layer having a metal-containing barrier layer, a metal-containing adhesion layer, and a metal layer.

39. The method of claim 29, wherein the sixth dielectric layer is selected from the group consisting of one or more layers of dielectric material, tantalum oxide, barium strontium titanate, silicon nitride, and oxide-nitride-oxide.

40. The method of claim 29, wherein the first conductive layer is of polysilicon.

41. The method of claim 29, wherein the fifth dielectric layer is a tunnel oxide.

42. A method of forming a portion of a memory array, the method comprising:

forming one or more isolation regions in a substrate, comprising;

forming a trench through a first dielectric layer formed on the substrate, through a second dielectric layer formed on the first dielectric layer, and into the substrate;

lining an interior of the trench with a layer of high-density plasma oxide, wherein the layer of high-density plasma oxide adjoins exposed portions of the first and second dielectric layers within the trench and exposed portions of the substrate within the trench;

forming a layer of spin-on dielectric material overlying the first and second dielectric layers and the layer of high-density plasma oxide such that the layer of spin-on dielectric material overfills the trench;

oxidizing the layer of spin-on dielectric material;

removing a portion of the oxidized layer of spin-on dielectric material to expose an upper surface of the second dielectric layer;

removing the second dielectric layer to expose an upper surface of the first dielectric layer so that portions of the layer of high-density plasma oxide material and the oxidized layer of spin-on dielectric material extend above the upper surface of the first dielectric layer; and

annealing at least the oxidized portion of the layer of spin-on dielectric material extending above the upper surface of the first dielectric layer;

removing the first dielectric layer after annealing at least the oxidized portion of the layer of spin-on dielectric material extending above the upper surface of the first dielectric layer to expose portions of the substrate on either side of each of the one or more isolation regions;

forming a third dielectric layer on the exposed portions of the substrate on either side of each of the one or more isolation regions;

forming a first conductive layer overlying the third dielectric layer;

forming a fourth dielectric layer overlying the first conductive layer and each of the one or more isolation regions; and

forming a second conductive layer overlying the fourth dielectric layer.

43. The method of claim 42, wherein the second dielectric layer is a nitride layer.

44. The method of claim 43, wherein removing the second dielectric layer comprises a dry etch.

45. The method of claim 42, wherein the second conductive layer is selected from the group consisting of refractory metals, refractory metal silicides, and a layer having a metal-containing barrier layer, a metal-containing adhesion layer, and a metal layer.

46. The method of claim 42, wherein the fourth dielectric layer is selected from the group consisting of one or more layers of dielectric material, tantalum oxide, barium strontium titanate, silicon nitride, and oxide-nitride-oxide.

47. The method of claim 42, wherein the first conductive layer is of polysilicon.

48. The method of claim 42, wherein the third dielectric layer is a tunnel oxide.

49. The method of claim 42, wherein the first dielectric layer is a pad oxide layer.

50. The method of claim 42, wherein the second dielectric layer is a nitride layer.

51. A method of forming a portion of a memory array, the method comprising:

forming one or more isolation regions in a semiconductor substrate, comprising;

forming a pad oxide layer overlying the semiconductor substrate;

forming a nitride layer overlying the pad oxide layer;

forming a trench through the pad oxide layer, through the nitride layer, and into the semiconductor substrate;

lining an interior of the trench with a layer of high-density plasma oxide, wherein the layer of high-density plasma oxide adjoins exposed portions of the pad oxide and nitride layers within the trench and exposed portions of the semiconductor substrate within the trench;

forming a layer of spin-on dielectric material overlying the pad oxide and nitride layers and the layer of high-density plasma oxide such that the layer of spin-on dielectric material overfills the trench;

oxidizing the layer of spin-on dielectric material;

removing a portion of the oxidized layer of spin-on dielectric material to expose an upper surface of the nitride layer;

removing the nitride layer, using a dry-etch process, to expose an upper surface of the pad oxide layer so that portions of the layer of high-density plasma oxide material and the oxidized layer of spin-on dielectric material extend above the upper surface of the pad oxide layer; and

annealing at least the oxidized portion of the layer of spin-on dielectric material extending above the upper surface of the pad oxide layer;

removing the pad oxide layer after annealing at least the oxidized portion of the layer of spin-on dielectric material extending above the upper surface of the pad oxide layer to expose portions of the substrate on either side of each of the one or more isolation regions;

forming a tunnel dielectric layer on the exposed portions of the substrate on either side of each of the one or more isolation regions;

forming a first conductive layer overlying the tunnel dielectric layer;

recessing each of the one or more isolation regions below an upper surface of the first conductive layer;

forming an interlayer dielectric layer overlying the first conductive layer and adjoining an exposed portion of each of the one or more isolation regions; and

forming a second conductive layer overlying the interlayer dielectric layer.

52. The method of claim 51, wherein the interlayer dielectric layer is selected from the group consisting of one or more layers of dielectric material, tantalum oxide, barium strontium titanate, silicon nitride, and oxide-nitride-oxide.

53. The method of claim 52, wherein the first conductive layer is of polysilicon.

54. The method of claim 53 wherein the second conductive layer is selected from the group consisting of refractory metals, refractory metal silicides, and a layer having a metal-containing barrier layer, a metal-containing adhesion layer, and a metal layer.

55. The method of claim 53, wherein the tunnel dielectric layer is a tunnel oxide.

56. A memory array, comprising:

a substrate;

a plurality of intersecting rows and columns formed on the substrate, each intersection of a row and column defining a memory cell; and

an isolation region disposed between adjacent columns of memory cells, wherein the isolation region comprises;

a layer of high-density plasma dielectric material formed within the substrate and adjoining the substrate; and

a second layer of dielectric material overlying the layer of high-density plasma dielectric material.

57. The memory array of claim 56, wherein the high-density plasma dielectric material is a high-density plasma oxide.

58. The memory array of claim 56, wherein the second layer of dielectric material is a densified spin-on dielectric material.

59. The memory array of claim 56, wherein the second layer of dielectric material comprises first and second materials that have been exposed to different levels of densification.

60. The memory array of claim 56, wherein each memory cell is a floating-gate memory cell.

61. The memory array of claim 56, wherein each memory cell is a flash memory cell.

62. A memory array, comprising:

a substrate;

a plurality of intersecting rows and columns formed on the substrate, each intersection of a row and column defining a non-volatile memory cell; and

an isolation region disposed between adjacent columns of non-volatile memory cells, wherein the isolation region comprises;

a layer of high-density plasma oxide formed within the substrate and adjoining the substrate; and

a layer of densified spin-on dielectric material having a first portion within the substrate and adjoining the layer of high-density plasma oxide and a second portion extending above an upper surface of the substrate between the memory cells of adjacent columns, wherein at least a portion of the first portion of the densified spin-on dielectric material has a lower densification level than the second portion of the densified spin-on dielectric material.

63. A memory module, comprising:

a plurality of contacts; and

two or more memory devices, each having access lines selectively coupled to the plurality of contacts;

wherein at least one of the memory devices comprises a memory array, comprising;

a plurality of intersecting rows and columns formed on a substrate, each intersection of a row and column defining a memory cell; and

an isolation region disposed between adjacent columns of memory cells, wherein the isolation region comprises;

a layer of high-density plasma dielectric material formed within the substrate and adjoining the substrate; and

a second layer of dielectric material overlying the layer of high-density plasma dielectric material.

64. The memory module of claim 63, wherein the memory cells are non-volatile memory cells.

65. The memory module of claim 63, wherein the high-density plasma dielectric material is a high-density plasma oxide.

66. The memory module of claim 63, wherein the second layer of dielectric material is a densified spin-on dielectric material.

67. The memory module of claim 63, wherein the second layer of dielectric material comprises first and second materials that have been exposed to different levels of densification.

68. A memory module, comprising:

a plurality of contacts; and

two or more memory devices, each having access lines selectively coupled to the plurality of contacts;

wherein at least one of the memory devices comprises a memory array, comprising;

a plurality of intersecting rows and columns formed on a substrate, each intersection of a row and column defining a non-volatile memory cell; and

an isolation region disposed between adjacent columns of memory cells, wherein the isolation region comprises;

a layer of high-density plasma oxide formed within the substrate and adjoining the substrate; and

a layer of densified spin-on dielectric material having a first portion within the substrate and adjoining the layer of high-density plasma dielectric material and a second portion extending above an upper surface of the substrate between the memory cells of adjacent columns, wherein at least a portion of the first portion of the densified spin-on dielectric material has a lower densification level than the second portion of the densified spin-on dielectric material.

69. A memory module, comprising:

a housing having a plurality of contacts; and

one or more memory devices enclosed in the housing and selectively coupled to the plurality of contacts;

wherein at least one of the memory devices comprises a memory array, comprising;

a plurality of intersecting rows and columns formed on a substrate, each intersection of a row and column defining a memory cell; and

an isolation region disposed between adjacent columns of memory cells, wherein the isolation region comprises;

a layer of high-density plasma dielectric material formed within the substrate and adjoining the substrate; and

a second layer of dielectric material overlying the layer of high-density plasma dielectric material.

70. A memory module, comprising:

a housing having a plurality of contacts; and

one or more memory devices enclosed in the housing and selectively coupled to the plurality of contacts;

wherein at least one of the memory devices comprises a memory array, comprising;

a plurality of intersecting rows and columns formed on a substrate, each intersection of a row and column defining a non-volatile memory cell; and

an isolation region disposed between adjacent columns of memory cells, wherein the isolation region comprises;

a layer of high-density plasma oxide formed within the substrate and adjoining the substrate; and

a layer of densified spin-on dielectric material having a first portion within the substrate and adjoining the layer of high-density plasma dielectric material and a second portion extending above an upper surface of the substrate between the memory cells of adjacent columns, wherein at least a portion of the first portion of the oxidized spin-on dielectric material has a lower densification level than the second portion of the densified spin-on dielectric material.

71. An electronic system, comprising:

a processor; and

one or more memory devices coupled to the processor, wherein at least one of the memory devices comprises a memory array, comprising;

a plurality of intersecting rows and columns formed on a substrate, each intersection of a row and column defining a memory cell; and

an isolation region disposed between adjacent columns of memory cells, wherein the isolation region comprises;

a layer of high-density plasma dielectric material formed within the substrate and adjoining the substrate; and

a second layer of dielectric material overlying the layer of high-density plasma dielectric material.

72. The electronic system of claim 71, wherein the memory cells are non-volatile memory cells.

73. The electronic system of claim 71, wherein the high-density plasma dielectric material is a high-density plasma oxide.

74. The electronic system of claim 71, wherein the second layer of dielectric material is a densified spin-on dielectric material.

75. The electronic system of claim 71, wherein the second layer of dielectric material comprises first and second materials that have been exposed to different levels of densification.

76. An electronic system, comprising:

a processor; and

one or more memory devices coupled to the processor, wherein at least one of the memory devices comprises a memory array, comprising;

a plurality of intersecting rows and columns formed on a substrate, each intersection of a row and column defining a non-volatile memory cell; and

an isolation region disposed between adjacent columns of memory cells,

wherein the isolation region comprises;

a layer of high-density plasma oxide formed within the substrate and adjoining the substrate; and

a layer of densified spin-on dielectric material having a first portion within the substrate and adjoining the layer of high-density plasma dielectric material and a second portion extending above an upper surface of the substrate between the memory cells of adjacent columns, wherein at least a portion of the first portion of the densified spin-on dielectric material has a lower densification level than the second portion of the densified spin-on dielectric material.