Semiconductor device and manufacturing method for the same

• US 20080014719A1
• Filed: 09/13/2007
• Published: 01/17/2008
• Est. Priority Date: 12/05/2003
• Status: Abandoned Application

• Current Assignee: ROHM Co., Ltd.
• Original Assignee: ROHM Co., Ltd.
• Inventors: SHIBATA, Kazutaka
• Application Number:
  US11/900,800
• Publication Number:
  US 20080014719A1
• Time in Patent Office: Days
• US Class Current: 438/460
• CPC Class Codes: H01L 21/02118 carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC polymers per se C08G, photoresist per se G03F
• CPC Class Codes: H01L 21/022 the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides adhesion layers or buffer layers H01L21/02304, H01L21/02362
• CPC Class Codes: H01L 21/02282 liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
• CPC Class Codes: H01L 21/312 Organic layers, e.g. photoresist H01L21/3105, H01L21/32 take precedence; photoresists per se G03C
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 2221/6834 used to protect an active side of a device or wafer
• CPC Class Codes: H01L 2223/5448 Located on chip prior to dicing and remaining on chip after dicing
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/274 by blanket deposition of the material of the layer connector
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/562 Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 2924/00011 Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]

Abstract

A semiconductor device has a semiconductor substrate having first and second surface, a first resin film formed on the first surface of the semiconductor substrate and a second resin film formed on the second surface of the semiconductor substrate. A projection electrode or an interconnection is formed on the first surface of the semiconductor substrate, the second resin film is made of low elastic resin which is capable of absorbing an impact applied to the second surface of the semiconductor substrate and the second resin film is thinner than the semiconductor substrate.

Claims

1-17. -17. (canceled)

18. A manufacturing method for a semiconductor device, comprising steps of:

forming a projection electrode or an interconnection on a first surface of a semiconductor substrate;

forming a first resin film on the first surface of the semiconductor substrate with low elastic resin which is tolerant against a physical deformation of the semiconductor substrate;

thinning the semiconductor substrate by polishing, grinding or chemically etching on a second surface of the semiconductor substrate;

forming a second resin film on the second surface of the semiconductor substrate; and

cutting the semiconductor substrate into individual pieces,

wherein the second resin film has an elastic modulus which is equivalent to that of the first resin film, and

the second resin film is thinner than the first resin film.

19. A manufacturing method for a semiconductor device as set forth in claim 18, wherein the first resin film covers the projection electrode or the interconnection.

20. A manufacturing method for a semiconductor device as set forth in claim 18, further comprising a step of:

putting a mark on the second surface of the semiconductor surface after thinning the semiconductor substrate.

21. A manufacturing method for a semiconductor device as set forth in claim 18, further comprising a step of:

thinning the first resin film so as to expose a top portion of the projection electrode or the interconnection after forming the second resin film.