System and method for on-board diagnostics of memory modules

• US 20080016401A1
• Filed: 09/17/2007
• Published: 01/17/2008
• Est. Priority Date: 08/19/2003
• Status: Active Grant

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Jeddeloh, Joseph
• Granted Patent: US 7,516,363 B2
• Time in Patent Office: Days
• US Class Current: 714/42
• CPC Class Codes: G11C 2029/5602 Interface to device under test
• CPC Class Codes: G11C 29/48 Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
• CPC Class Codes: G11C 29/56 External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
• CPC Class Codes: G11C 29/56004 Pattern generation
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports

Abstract

A memory hub includes an on-board diagnostic engine through which diagnostic testing and evaluation of the memory system can be performed. The memory hub includes a link interface for receiving memory requests for access to memory devices of the memory system and a memory device interface coupled to the memory devices for coupling memory requests to the memory devices. A memory hub diagnostic engine is coupled through a switch to the link interface and the memory device interface to perform diagnostic testing of the memory system. The diagnostic engine includes a maintenance port that provides access to results of the diagnostic testing and through which diagnostic testing commands can be received.

Claims

1-32. -32. (canceled)

33. A memory test system for testing a system memory of a computer, comprising:

a host computer system operable to provide diagnostic testing commands; and

a system memory under test having a plurality of memory modules, each of the memory modules having a plurality of memory devices and a memory hub coupled to the memory devices, the memory hub comprising;

a memory device interface coupled to the memory devices of the respective memory module, the memory device interface operable to provide signals to the memory devices and further operable to receive signals from the memory devices; and

a diagnostic test engine coupled to the memory device interface and having a host computer system interface coupled to the host computer system and operable to receive the diagnostic testing commands, the diagnostic test engine operable to monitor memory system operation while at least one of the memory devices is operating.

34. The memory test system of claim 33, wherein the host computer system is further operable to receive diagnostic testing results, and the diagnostic test engine is further operable to provide the diagnostic testing results.

35. The memory test system of claim 34, wherein the diagnostic testing results comprise results from monitoring the memory system operation.

36. The memory test system of claim 33 wherein the monitoring memory system operation includes monitoring signals transmitted to or received from the memory devices.

37. The memory test system of claim 36, wherein the diagnostic testing results comprise results from monitoring the signals.

38. The memory test system of claim 33 wherein the diagnostic engine of the memory hub comprises:

a maintenance port interface operable to translate the diagnostic testing commands into control signals for the diagnostic test engine;

a pattern generator coupled to the maintenance port interface and operable to generate test patterns for diagnostic testing of the memory devices in response to receiving control signals from the maintenance port interface;

a sequencer coupled to the maintenance port interface operable to access the memory devices, the sequencer generating memory commands based on the control signals received from the maintenance port interface; and

a memory device interface controller coupled to the maintenance port and further coupled to the memory device interface, the memory device interface controller operable to monitor the transmission of signals to the memory devices and the reception of data signals from the memory devices.

39. The memory test system of claim 33 wherein the diagnostic test engine of the memory hub comprises a diagnostic test engine operable to monitor at least one of signal timing and voltage margin of signals sent to the memory devices.

40. The memory test system of claim 33 wherein the diagnostic test engine of the memory hub comprises a diagnostic test engine operable to control transmission and reception of signals by the memory device interface.

41. The memory test system of claim 40 wherein the memory device interface includes transmitter and receiver logic and wherein the diagnostic test engine of the memory hub comprises a diagnostic test engine operable to control at least one of drive strength and slew rate of the transmitter logic, and filter coefficients of the receiver logic.

42. The memory test system of claim 33 wherein the memory hub further comprises a direct memory access (DMA) engine coupled to the diagnostic test engine, the DMA engine operable to retrieve and load data patterns for testing into the memory hub.

43. The memory test system of claim 42 wherein the DMA engine comprises a DMA engine further operable to store signal trace history for at least one of the signals sent to the memory devices for retrieval through the host computer system interface.

44. A memory test system for testing a system memory of a computer, comprising:

a host computer system operable to provide diagnostic testing commands and receive diagnostic testing results; and

a system memory under test having a plurality of memory modules coupled to a link on which signals are transmitted, each of the memory modules having located thereon a plurality of memory devices and a memory hub coupled to the memory devices, the memory hub comprising;

a plurality of link interfaces coupled to the link, the link interfaces operable to transmit and receive signals on the link; and

a diagnostic test engine coupled to the link interface and having a host computer system interface coupled to the host computer system and operable to receive the diagnostic testing commands and provide diagnostic testing results, the diagnostic test engine operable to monitor memory system operation, the diagnostic test engine further operable to provide results from monitoring the memory system operation to the host computer system as diagnostic testing results.

45. The memory test system of claim 44 wherein the diagnostic engine of the memory hub comprises:

a maintenance port interface operable to translate the diagnostic testing commands into control signals for the diagnostic test engine;

a pattern generator coupled to the maintenance port interface and operable to generate test patterns for diagnostic testing of the memory devices in response to receiving control signals from the maintenance port interface;

a sequencer coupled to the maintenance port interface operable to access the memory devices, the sequencer generating memory commands based on the control signals received from the maintenance port interface; and

a link interface controller coupled to the maintenance port and further coupled to the link interface, the link interface controller operable to monitor the transmission of at least one of control, address, and data signals on the link.

46. The memory test system of claim 44 wherein the diagnostic test engine is operable to monitor at least one of signal timing and voltage margin of at least one of control, address, and data signals.

47. The memory test system of claim 44 wherein the diagnostic test engine is operable to control transmission and reception of signals by at least one of the link interfaces.

48. The memory test system of claim 44 wherein the link interfaces include transmitter and receiver logic and wherein the diagnostic test engine of the memory hub comprises a diagnostic test engine operable to control at least one of drive strength and slew rate of the transmitter logic, and filter coefficients of the receiver logic.

49. The memory test system of claim 44 wherein the memory hub further comprises a direct memory access (DMA) engine coupled to the diagnostic test engine, the DMA engine operable to retrieve and load data patterns for testing into the memory hub.

50. The memory test system of claim 44 wherein the DMA engine comprises a DMA engine further operable to store signal trace history for at least one of the control, address, and data signals for retrieval through the host computer system interface.

51. A method for evaluating performance of a memory hub based memory module having a plurality of memory devices coupled to the memory hub, the method comprising:

providing diagnostic testing commands to a diagnostic engine embedded in the memory hub of the memory module to perform diagnostic testing;

controlling a link interface circuit to monitor signals transmitted or received on a link to which the memory hub of the memory module is coupled;

controlling a memory device interface circuit to monitor signals during transmission to or reception from the memory devices;

storing the results of monitoring by the memory device interface circuit and the results of monitoring by the link interface circuits in a memory;

providing diagnostic testing commands to the diagnostic engine embedded in the memory hub to retrieve the stored results and provide the results over a maintenance port of the diagnostic engine.

52. The method of claim 51 wherein controlling the memory device interface circuit to monitor signals during transmission to or reception from the memory devices comprises controlling the memory device interface circuit to monitor at least one of signal timing and voltage margin of signals.

53. The method of claim 51 wherein controlling the link interface circuit to monitor signals transmitted or received on a link to which the memory hub of the memory module is coupled comprises controlling the link interface circuits to monitor at least one of signal timing and voltage margin of the signals.

54. The method of claim 51 wherein controlling the memory device interface circuit to monitor signals during transmission to or reception from the memory devices comprises controlling at least one of drive strength and slew rate of transmitter logic of the memory device interface, and filter coefficients of receiver logic of the memory device interface.

55. The method of claim 51 wherein controlling the link interface circuit to monitor signals transmitted or received on a link to which the memory hub of the memory module is coupled comprises controlling at least one of drive strength and slew rate of transmitter logic of the link interface, and filter coefficients of receiver logic of the link interface.