Semiconductor memory device and bit error detection method thereof
First Claim
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1. A semiconductor memory device comprising:
- a cyclic redundancy check (CRC) circuit generating a write CRC code corresponding to data to be stored in memory cells; and
an error correction code (ECC) circuit generating an ECC code corresponding to the data and detecting and correcting a bit error of the data by means of the ECC code during a read operation, wherein the CRC circuit generates a read CRC code corresponding to data corrected by the ECC circuit during the read operation, and corrects a bit error of the data according to a comparison of the read CRC code and the write CRC code.
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Abstract
A memory device detects and corrects bit errors. The memory device includes cyclic redundancy check (CRC) and error correction code (ECC) circuits. The CRC circuit generates a write CRC code corresponding to data to be stored in memory cells. The ECC circuit generates an ECC code corresponding to the data and detecting and correcting a bit error of the data by means of the ECC code during a read operation. The CRC circuit generates a read CRC code corresponding to data corrected by the ECC circuit during the read operation, and corrects a bit error of the data according to a comparison of the read CRC code and the write CRC code.
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20 Claims
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1. A semiconductor memory device comprising:
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a cyclic redundancy check (CRC) circuit generating a write CRC code corresponding to data to be stored in memory cells; and
an error correction code (ECC) circuit generating an ECC code corresponding to the data and detecting and correcting a bit error of the data by means of the ECC code during a read operation, wherein the CRC circuit generates a read CRC code corresponding to data corrected by the ECC circuit during the read operation, and corrects a bit error of the data according to a comparison of the read CRC code and the write CRC code. - View Dependent Claims (2, 3, 4, 5)
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6. A semiconductor memory device comprising:
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a cyclic redundancy check (CRC) circuit generating a write CRC code corresponding to data to be stored in memory cells;
a first error correction code (ECC) circuit generating a first ECC code corresponding to the data and detecting and correcting a bit error of the data by means of the first ECC code during a read operation; and
a second ECC circuit generating a second ECC code corresponding to the write CRC data and detecting and correcting a bit error of the write CRC code by means of the second ECC code during the read operation, wherein the CRC circuit generates a read CRC code corresponding to data corrected by the first ECC circuit during the read operation, and corrects a bit error of the data according to a comparison of the read CRC code and the write CRC code corrected by the second ECC circuit. - View Dependent Claims (7, 8, 9, 10, 11)
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12. A method of detecting a bit error in a semiconductor memory device, comprising:
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generating error correction code (ECC) and cyclic redundancy check (CRC) codes corresponding to data to be stored in memory cells;
storing the data in the memory cells;
correcting a bit error for the data stored in the memory cells by means of the ECC code;
generating a read CRC code corresponding to the data corrected with the bit error; and
detecting a bit error of the data according to a comparison of the read CRC code to the write CRC code. - View Dependent Claims (13, 14, 15, 16)
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17. A method of detecting a bit error in a semiconductor memory device, comprising:
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generating a write cyclic redundancy check (CRC) code corresponding to data to be stored in memory cells;
generating a first error correction code (ECC) code corresponding to the data to be stored in the memory cells, and a second ECC code corresponding to the write CRC code;
programming the data, the write CRC code, and the first and second ECC codes into the memory cells;
correcting a bit error of the data by means of the first ECC code, and a bit error of the write CRC code by means of the second ECC code;
generating a read CRC code corresponding to the data corrected with the bit error; and
detecting a bit error of the data according to a comparison of the read CRC code and the write CRC code corrected with the bit error. - View Dependent Claims (18, 19, 20)
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Specification