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Semiconductor memory device and bit error detection method thereof

  • US 20080016428A1
  • Filed: 10/17/2006
  • Published: 01/17/2008
  • Est. Priority Date: 10/24/2005
  • Status: Abandoned Application
First Claim
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1. A semiconductor memory device comprising:

  • a cyclic redundancy check (CRC) circuit generating a write CRC code corresponding to data to be stored in memory cells; and

    an error correction code (ECC) circuit generating an ECC code corresponding to the data and detecting and correcting a bit error of the data by means of the ECC code during a read operation, wherein the CRC circuit generates a read CRC code corresponding to data corrected by the ECC circuit during the read operation, and corrects a bit error of the data according to a comparison of the read CRC code and the write CRC code.

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