PARASITIC IMPEDANCE ESTIMATION IN CIRCUIT LAYOUT

• US 20080016478A1
• Filed: 07/12/2007
• Published: 01/17/2008
• Est. Priority Date: 08/18/2003
• Status: Abandoned Application

• Current Assignee: CRAY Incorporated (Hewlett-Packard Enterprise Company)
• Original Assignee: CRAY Incorporated (Hewlett-Packard Enterprise Company)
• Inventors: Lutz, Robert, Ficke, Joel
• Application Number:
  US11/777,094
• Publication Number:
  US 20080016478A1
• Time in Patent Office: Days
• US Class Current: 716/5
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods

Abstract

The present invention in one embodiment performs estimation of parasitic impedances in a circuit. Leaf cells of circuit components are evaluated such that their parasitic impedances are estimated, and the leaf cells are placed in a physical layout. Parasitic impedances of interconnect wiring is evaluated, and the interconnect wire routing is placed. Parasitic impedance within the circuit is then estimated using a parasitic reduction process.

Claims

1. A method of estimating parasitic impedances in a circuit, comprising:

estimating leaf cell parasitic impedances for at least one node of two or more leaf cells;

placing the two or more leaf cells in a physical layout;

estimating interconnect wiring parasitic impedances;

placing interconnect wire routing linking nodes of at least two of the two or more leaf cells; and

estimating parasitic impedances of the circuit using parasitic reduction after estimating parasitic impedances and placing the two or more leaf cells and the interconnect wiring.

2. The method of claim 1, wherein the estimating leaf cell parasitic impedances;

placing leaf cells in a physical layout, and estimating interconnect wiring parasitic impedances are performed before performing interconnect wire routing.

3. The method of claim 1, wherein placing interconnect wiring parasitic impedances and placing interconnect wire routing are repeated until satisfactory wiring parasitic impedances are obtained.

4. The method of claim 1, wherein an area wire load model is used to estimate interconnect wiring parasitic impedances.

5. The method of claim 1, wherein a shortest manhattan distance model is used to estimate interconnect wiring parasitic impedances.

6. The method of claim 1, wherein parasitic impedances are estimated for multiple interconnect wire routings.

7. The method of claim 1, wherein parasitic impedances are estimated for multiple leaf cell physical layouts.

8. The method of claim 1, further comprising running a circuit performance test using the estimated parasitic impedances of the circuit.

9. A machine-readable medium with instructions stored thereon, the instructions when executed operable to cause a computerized system to:

estimate leaf cell parasitic impedances for at least one node of two or more leaf cells;

place the two or more leaf cells in a physical layout;

estimate interconnect wiring parasitic impedances;

place interconnect wire routing linking nodes of at least two of the two or more leaf cells; and

estimate parasitic impedances of the circuit using parasitic reduction after estimating parasitic impedances and placing the two or more leaf cells and the interconnect wiring.

10. The method of claim 9, wherein the estimating leaf cell parasitic impedances;

placing leaf cells in a physical layout, and estimating interconnect wiring parasitic impedances are performed before performing interconnect wire routing.

11. The method of claim 9, wherein placing interconnect wiring parasitic impedances and placing interconnect wire routing are repeated until satisfactory wiring parasitic impedances are obtained.

12. The method of claim 9, wherein an area wire load model is used to estimate interconnect wiring parasitic impedances.

13. The method of claim 9, wherein a shortest Manhattan distance model is used to estimate interconnect wiring parasitic impedances.

14. The method of claim 9, wherein parasitic impedances are estimated for multiple interconnect wire routings.

15. The method of claim 9, wherein parasitic impedances are estimated for multiple leaf cell physical layouts.

16. The method of claim 9, the instructions when executed further operable to cause the computerized system to run a circuit performance test using the estimated parasitic impedances of the circuit.

17. An electronic circuit layout system, comprising elements for:

estimating leaf cell parasitic impedances for at least one node of two or more leaf cells;

placing the two or more leaf cells in a physical layout;

estimating interconnect wiring parasitic impedances;

placing interconnect wire routing linking nodes of at least two of the two or more leaf cells; and

estimating parasitic impedances of the circuit using parasitic reduction after estimating parasitic impedances and placing the two or more leaf cells and the interconnect wiring.

18. The electronic circuit layout system of claim 17, wherein the estimating leaf cell parasitic impedances;

placing leaf cells in a physical layout, and estimating interconnect wiring parasitic impedances are performed before performing interconnect wire routing.

19. The electronic circuit layout system of claim 17, wherein placing interconnect wiring parasitic impedances and placing interconnect wire routing are repeated until satisfactory wiring parasitic impedances are obtained.

20. The electronic circuit layout system of claim 17, wherein an area wire load model is used to estimate interconnect wiring parasitic impedances.

21. The electronic circuit layout system of claim 17, wherein a shortest manhattan distance model is used to estimate interconnect wiring parasitic impedances.

22. The electronic circuit layout system of claim 17, wherein parasitic impedances are estimated for multiple interconnect wire routings.

23. The electronic circuit layout system of claim 17, wherein parasitic impedances are estimated for multiple leaf cell physical layouts.

24. The electronic circuit layout system of claim 17, further comprising running a circuit performance test using the estimated parasitic impedances of the circuit.

25. A method of estimating parasitic impedances in a circuit, comprising:

estimating average parasitic impedances per wire length;

determining the area of a circuit;

estimating an average wire length per circuit area; and

applying the estimated parasitic impedances per wire length and the estimated average wire length per circuit area to the determined area of a circuit to estimate the circuit'"'"'s parasitic impedance.

26. The method of estimating parasitic impedances in a circuit of claim 25, further comprising estimating parasitic impedances of the circuit using parasitic reduction.

27. The method of claim 25, wherein the circuit comprises a leaf cell.

28. The method of claim 25, further comprising estimating the parasitic impedance of one or more nets within the circuit by applying a model based on physical dimensions of the one or more nets and known parasitic impedances of nets of known physical dimensions;

and

incorporating the estimated parasitic impedances of the one or more nets within the circuit into the estimated parasitic impedances in the circuit.