System and Method for Driving Values to DC Adjusted/Untimed Nets to Identify Timing Problems

• US 20080016480A1
• Filed: 07/17/2006
• Published: 01/17/2008
• Est. Priority Date: 07/17/2006
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Ja, Yee, Gass, Robert B., Jaeschke, Christoph
• Granted Patent: US 7,490,305 B2
• Time in Patent Office: Days
• US Class Current: 716/6
• CPC Class Codes: G06F 30/3312 Timing analysis

Abstract

A system and method for driving values to “don'"'"'t care” (DC) adjusted/untimed nets of an integrated circuit design to thereby identify timing problems are provided. The system and method may be utilized, for example, with logical built-in self test (LBIST) testing of an integrated circuit in which the DC adjusted (dcadj) nets for normal functional mode of the integrated circuit may not be DC adjusted for LBIST mode. By using the system and method, timing related problems associated with DC adjusted/untimed nets can be made apparent either by using simulation or semi-formal/formal analysis. For example, with regard to DC adjusted/untimed nets, the system and method may identify any violations of these nets with regard to maintaining their DC adjusted values. Such identification of violations of DC adjusted/untimed nets may be made without interfering with the static timing analysis of timed nets.

Claims

1. A method, in a data processing device, for verifying an operation of untimed net segments of an integrated circuit design, comprising:

receiving the integrated circuit design;

identifying at least one untimed net segment in the integrated circuit design;

driving a value along a pathway to the at least one untimed net segment;

collecting an output value from the untimed net segment; and

verifying an operation of the untimed net segment of the integrated circuit design based on the collected output value from the untimed net segment.

2. The method of claim 1, wherein the operation of the untimed net segment is verified if the output value from the untimed net segment maintains a predetermined value.

3. The method of claim 1, wherein the operation of the untimed net segment is not verified if the output value from the untimed net segment achieves a value different from a predetermined value.

4. The method of claim 1, further comprising:

replicating, in the integrated circuit design, a pathway to the untimed net segment, wherein driving the value along a pathway to the at least one untimed net segment comprises driving the value along the replicated pathway to the untimed net segment.

5. The method of claim 1, wherein identifying at least one untimed net segment in the integrated circuit design comprises:

receiving a “

don'"'"'t care”

(DC) adjusted list data structure that identifies net segments that do not need to adhere to timing requirements;

comparing entries in the DC adjusted list data structure to a netlist for the integrated circuit design; and

identifying at least one untimed net segment based on a match of a net segment in the DC adjusted list data structure with a net in the netlist for the integrated circuit design.

6. The method of claim 1, wherein driving a value along a pathway to the at least one untimed net segment comprises:

driving one of an indeterminate value or a random value along the pathway to the at least one untimed net segment; and

performing one of formal, semi-formal, or non-formal verification analysis on the integrated circuit design using the driven value.

7. The method of claim 6, wherein the verification analysis uses a logical built-in self test mode of operation of the integrated circuit device.

8. The method of claim 3, further comprising:

outputting a result of the verification, wherein the result identifies untimed net segments that are not verified as maintaining the predetermined value.

9. The method of claim 1, wherein an indeterminate value is driven along the pathway to the at least one untimed net segment, and wherein if the collected output value from the untimed net is an indeterminate value, the untimed net segment is determined to be invalid.

10. The method of claim 5, further comprising:

automatically modifying the DC adjusted list data structure based on results of the verification.

11. A computer program product comprising a computer useable medium having a computer readable program, wherein the computer readable program, when executed on a computing device, causes the computing device to:

receive an integrated circuit design;

identify at least one untimed net segment in the integrated circuit design;

drive a value along a pathway to the at least one untimed net segment;

collect an output value from the untimed net segment; and

verify an operation of the untimed net segment of the integrated circuit design based on the collected output value from the untimed net segment.

12. The computer program product of claim 11, wherein the operation of the untimed net segment is verified if the output value from the untimed net segment maintains a predetermined value.

13. The computer program product of claim 11, wherein the operation of the untimed net segment is not verified if the output value from the untimed net segment achieves a value different from a predetermined value.

14. The computer program product of claim 11, wherein the computer readable program further causes the computing device to replicate, in the integrated circuit design, a pathway to the untimed net segment, and wherein the computer readable program causes the computing device to drive the value along a pathway to the at least one untimed net segment by driving the value along the replicated pathway to the untimed net segment.

15. The computer program product of claim 11, wherein the computer readable program causes the computing device to identify at least one untimed net segment in the integrated circuit design by:

receiving a “

don'"'"'t care”

(DC) adjusted list data structure that identifies net segments that do not need to adhere to timing requirements;

comparing entries in the DC adjusted list data structure to a netlist for the integrated circuit design; and

identifying at least one untimed net segment based on a match of a net segment in the DC adjusted list data structure with a net in the netlist for the integrated circuit design.

16. The computer program product of claim 11, wherein the computer readable program causes the computing device to drive a value along a pathway to the at least one untimed net segment by:

driving one of an indeterminate value or a random value along the pathway to the at least one untimed net segment; and

performing one of formal, semi-formal, or non-formal verification analysis on the integrated circuit design using the driven value.

17. The computer program product of claim 16, wherein the verification analysis uses a logical built-in self test mode of operation of the integrated circuit device.

18. The computer program product of claim 13, wherein the computer readable program further causes the computing device to:

output a result of the verification, wherein the result identifies untimed net segments that are not verified as maintaining the predetermined value.

19. The computer program product of claim 11, wherein an indeterminate value is driven along the pathway to the at least one untimed net segment, and wherein if the collected output value from the untimed net is an indeterminate value, the untimed net segment is determined to be invalid.

20. An apparatus, comprising:

a processor; and

a memory coupled to the processor, wherein the memory contains instructions which, when executed by the processor, cause the processor to;

receive an integrated circuit design;

identify at least one untimed net segment in the integrated circuit design;

drive a value along a pathway to the at least one untimed net segment;

collect an output value from the untimed net segment; and

verify an operation of the untimed net segment of the integrated circuit design based on the collected output value from the untimed net segment.