Method for Protecting a Logic or Mathematical operator Installed in an Electronic Module with a Microprocessor, as well as the Associated Embarked Electronic Module and the System

• US 20080016583A1
• Filed: 12/20/2001
• Published: 01/17/2008
• Est. Priority Date: 12/21/2000
• Status: Active Grant

• Current Assignee: Thales DIS France SA
• Original Assignee: Gemalto SA (Thales SA)
• Inventors: Giraud, Nicolas, Brohl, Abraham, Hameau, Patrice
• Granted Patent: US 9,323,955 B2
• Time in Patent Office: Days
• US Class Current: 726/34
• CPC Class Codes: G06F 21/755 with measures against power attack

Abstract

The method for protecting a logic or mathematical operator of the NOR operator type, able to be used for executing a program in a microprocessor electronic module wherein the execution of the NOR operator is replaced by the execution (CAL-XORSEC(1) of a sequence Si operations having for final result a result identical to that of the XOR function.

The sequence of operations Si composed of elementary operations with AND, OR and NOT is selected at each XOR operator from a set of eight equivalent sequences (S1 to S8) after determination CAL-NDO) of an order number NDO=1 according to the parameters of the program and/or a random parameter R supplied by a pseudo-random number generator (14).

Claims

1. Method for protecting a logic or mathematical operator or a similar functional circuit able to be used for executing a program in an electronic module with a processor, wherein the execution of said operator is replaced by a sequence of replacement operations whose or final result is identical to that of the function of said operator.

2. Method according to claim 1, wherein said sequence of replacement operations is selected on each call from said operator from a set of equivalent sequences.

3. Method according to claim 2, wherein the order number in said set of the selected sequence is determined according to certain parameters of the program being executed and/or a random parameter obtained from a pseudo-random number generator.

4. Method according to claim 2, wherein certain sequences include at least one non-operative instruction intended for introducing a delay time in the execution of the sequences in question, said non-operative instruction being selected from non-operative instructions in relation to the microprocessor or from instructions which are normally operative but rendered ineffective via their positions in the in the sequence of operations.

5. Method according to claim 2, wherein at least one sequence of replacement operations is made up of elementary logic operators.

6. Method according to claim 5, wherein at least one sequence of replacement operations is made up of AND, OR and NOT elementary logic operators.

7. Electronic module including at least one microprocessor and one program to be executed and including at least one logic or mathematical operator or similar functional circuit to be protected, wherein the module includes means for replacing the execution of said operator by the execution of a sequence of operations whose final result is identical to that of the function of said operator.

8. Electronic module according to claim 7, wherein it includes means for selecting said sequence of operations on each call of said operator from a set of equivalent sequences.

9. Electronic module according to claim 8, wherein it includes data processing means so as to determine the order number in said set of the selected sequence according to certain parameters of the program being executed and/or a random parameter generated by a pseudo-random numbers generator.

10. Installed system, wherein it includes an electronic module according to claim 7.