SOI DEVICE AND METHOD FOR ITS FABRICATION

• US 20080017906A1
• Filed: 07/21/2006
• Published: 01/24/2008
• Est. Priority Date: 07/21/2006
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Wu, Donggang D., Buller, James F., Pelella, Mario M.
• Granted Patent: US 7,718,503 B2
• Time in Patent Office: Days
• US Class Current: 257/306
• CPC Class Codes: H01L 21/743 Making of internal connections, substrate contacts
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/0255 using diodes as protective elements
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688

Abstract

A silicon on insulator (SOI) device and methods for fabricating such a device are provided. The device includes an MOS capacitor coupled between voltage busses and formed in a monocrystalline semiconductor layer overlying an insulator layer and a semiconductor substrate. The device includes at least one electrical discharge path for discharging potentially harmful charge build up on the MOS capacitor. The MOS capacitor has a conductive electrode material forming a first plate of the MOS capacitor and an impurity doped region in the monocrystalline silicon layer beneath the conductive electrode material forming a second plate. A first voltage bus is coupled to the first plate of the capacitor and to an electrical discharge path through a diode formed in the semiconductor substrate and a second voltage bus is coupled to the second plate of the capacitor.

Claims

1. A method for fabricating a semiconductor on insulator (SOI) device comprising a semiconductor substrate, a buried insulator layer overlying the semiconductor substrate, and a monocrystalline semiconductor layer overlying the buried insulator layer, the method comprising the steps of:

forming an MOS capacitor coupled between a first voltage bus and a second voltage bus, the MOS capacitor having a gate electrode material forming a first plate of the MOS capacitor and coupled to the first voltage bus and an impurity doped region in the monocrystalline semiconductor layer beneath the gate electrode material forming a second plate of the MOS capacitor and coupled to the second bus; and

forming an electrical discharge path coupling the first plate of the MOS capacitor to a diode formed in the semiconductor substrate.

2. The method of claim 1 wherein the step of forming an electrical discharge path comprises the steps of:

forming a dielectric isolation region extending through the monocrystalline semiconductor layer to the buried insulator layer;

etching an opening through the dielectric isolation region and the buried insulation layer to expose a portion of the semiconductor substrate;

ion implanting first type conductivity determining impurities through the opening to form a PN junction diode in the semiconductor substrate; and

coupling the first voltage bus to the PN junction diode in the semiconductor substrate.

3. The method of claim 2 further comprising the steps of:

etching a second opening through a dielectric isolation region and the buried insulation layer to expose a second portion of the semiconductor substrate;

ion implanting second type conductivity determining impurities through the opening to form a contact to the semiconductor substrate; and

coupling the second voltage bus to the contact to the semiconductor substrate.

4. The method of claim 1 further comprising the step of forming a second electrical discharge path coupling the second plate of the MOS capacitor to the semiconductor substrate.

5. A method for fabricating a semiconductor on insulator (SOI) device comprising a P-type semiconductor substrate, a buried insulator layer overlying the P-type semiconductor substrate, and a monocrystalline semiconductor layer overlying the buried insulator layer, the method comprising the steps of:

forming dielectric isolation regions extending through the monocrystalline semiconductor layer;

etching an opening extending through one of the dielectric isolation regions and the buried insulator layer to expose a portion of the P-type semiconductor substrate;

doping the portion of the P-type semiconductor substrate exposed through the opening with N-type impurities to form an N-type region forming a PN junction diode with the P-type semiconductor substrate;

doping a portion of the monocrystalline semiconductor layer with N-type impurity dopants to form a first plate of a capacitor;

forming an insulator layer overlying the portion of the monocrystalline semiconductor layer;

forming a conductive electrode overlying the insulator layer to form a second plate of the capacitor;

coupling a first bus to the second plate of the capacitor and to the N-type region; and

coupling a second bus to the first plate of the capacitor.

6. The method of claim 5 further comprising the steps of:

etching a second opening extending through one of the dielectric regions and the buried insulator layer to expose a second portion of the P-type semiconductor substrate;

doping the second portion of the P-type semiconductor substrate with P-type impurities to form a contact to the P-type semiconductor substrate; and

coupling the second bus to the first plate of the capacitor and to the contact to the P-type semiconductor substrate.

7. The method of claim 5 wherein the step of forming a conductive electrode comprises the steps of:

depositing a layer of polycrystalline silicon overlying the insulator layer; and

patterning the layer of polycrystalline silicon to form a conductive electrode, a gate electrode of an NMOS transistor, and a gate electrode of a PMOS transistor.

8. The method of claim 7 wherein the step of doping the second portion of the P-type semiconductor substrate further comprises the step of forming source and drain regions of the PMOS transistor.

9. The method of claim 7 wherein the step of doping the portion of the P-type semiconductor substrate further comprises the step of forming source and drain regions of the NMOS transistor.

10. A method for fabricating a semiconductor component including a semiconductor on insulator (SOI) substrate having a first p-type semiconductor layer, a layer of insulator on the first p-type semiconductor layer, and a second semiconductor layer overlying the layer of insulator, the method comprising the steps of:

implanting n-type conductivity determining ions into the second semiconductor layer to form a drain region of an MOS transistor;

implanting n-type conductivity determining ions into the first semiconductor layer to form an n-type impurity doped region forming a pn junction diode with the first p-type semiconductor layer; and

depositing and patterning a metal layer to form a first voltage bus coupled to the drain region and to the n-type impurity doped region.

11. The method of claim 10 further comprising the steps of:

depositing a first layer of insulating material overlying the second semiconductor layer;

etching the first layer of insulating material to form a first opening extending through the first layer of insulating material and exposing a portion of the drain region and a second opening exposing a portion of the n-type impurity doped region;

depositing a first layer of metal overlying the first layer of insulating material and electrically contacting the portion of the drain region and electrically contacting the portion of the impurity doped region; and

patterning the first layer of metal to form a first interconnect electrically coupled to the portion of the drain region and a second interconnect electrically coupled to the portion of the impurity doped region.

12. The method of claim 11 further comprising the steps of:

depositing a second layer of insulating material overlying the first interconnect and the second interconnect;

etching a third opening extending through the second layer of insulating material and exposing a portion of the first interconnect; and

etching a fourth opening extending through the second layer of insulating material and exposing a portion of the second interconnect.

13. The method of claim 12 wherein the step of depositing and patterning a metal layer comprises the steps of:

depositing a second layer of metal overlying the second layer of insulating material and electrically coupled to the first interconnect and to the second interconnect; and

patterning the second layer of metal to form a voltage bus coupled to the first interconnect and to the second interconnect.

14. The method of claim 10 further comprising the steps of:

forming an n-type region in the second semiconductor layer;

forming a capacitor dielectric layer overlying the n-type region in the second semiconductor layer;

forming a top capacitor plate overlying the capacitor dielectric layer; and

coupling the first voltage bus to the top capacitor plate.

15. The method of claim 14 wherein the step of depositing and patterning a metal layer further comprises the step of patterning the metal layer to form a second voltage bus coupled to the n-type region in the second semiconductor layer.

16. The method of claim 15 further comprising the steps of:

forming a contact area in the first p-type semiconductor layer; and

coupling the second voltage bus to the contact area.

17. A semiconductor on insulator (SOI) device comprising:

a semiconductor substrate;

a buried insulator layer overlying the semiconductor substrate;

a monocrystalline semiconductor layer overlying the buried insulator layer;

an MOS capacitor comprising;

an impurity doped region in the monocrystalline semiconductor layer forming a first plate of the MOS capacitor;

a dielectric layer overlying the impurity doped region; and

a conductive material overlying the dielectric layer and forming a second plate of the MOS capacitor;

a PN junction diode formed in the semiconductor substrate;

a first voltage bus coupled to the first plate; and

a second voltage bus coupled to the second plate and to the PN junction diode.

18. The semiconductor on insulator (SOI) device of claim 17 further comprising:

an electrical contact to the semiconductor substrate; and

an interconnect coupling the electrical contact to the first voltage bus.

19. The semiconductor on insulator (SOI) device of claim 18 further comprising:

a PMOS transistor formed in a first electrically isolated portion of the monocrystalline semiconductor layer;

an NMOS transistor formed in a second electrically isolated portion of the monocrystalline semiconductor layer; and

wherein the MOS capacitor is formed in a third electrically isolated portion of the monocrystalline semiconductor layer.

20. The semiconductor on insulator (SOI) device of claim 19 wherein a drain of the PMOS transistor is coupled to the first voltage bus and a drain of the NMOS transistor is coupled to the second voltage bus.