Structures of high-voltage MOS devices with improved electrical performance

• US 20080017948A1
• Filed: 10/26/2006
• Published: 01/24/2008
• Est. Priority Date: 07/21/2006
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Huang, Kun-Ming, Chou, Hsueh-Liang, Wu, Chen-Bau, Chu, Weng-Chu
• Granted Patent: US 7,888,767 B2
• Time in Patent Office: Days
• US Class Current: 257/487
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/1045 the doping structure being parallel to the channel length, e.g. DMOS like
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/1087 characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

A semiconductor structure includes a first high-voltage well (HVW) region of a first conductivity type overlying a substrate, a second HVW region of a second conductivity type opposite the first conductivity type overlying the substrate and laterally adjoining the first HVW region, and a third HVW region of the second conductivity type underlying the second HVW region. A region underlying the first HVW region is substantially free from the third HVW region, wherein the third HVW region has a bottom lower than a bottom of the first HVW region. The semiconductor structure further includes an insulation region in a portion and extending from a top surface of the first HVW region into the first HVW region, a gate dielectric extending from over the first HVW region to over the second HVW region wherein the gate dielectric has a portion over the insulation region, and a gate electrode on the gate dielectric.

Claims

1. A semiconductor structure comprising:

a substrate;

a first high-voltage well (HVW) region of a first conductivity type overlying the substrate;

a second HVW region of a second conductivity type opposite the first conductivity type overlying the substrate and laterally adjoining the first HVW region;

a third HVW region of the second conductivity type underlying the second HVW region, wherein a region underlying the first HVW region is substantially free from the third HVW region, and wherein the third HVW region has a bottom substantially lower than a bottom of the first HVW region;

an insulation region in a portion of the first HVW regions and extending from a top surface of the first HVW region into the first HVW region;

a gate dielectric extending from over the first HVW region to over the second HVW region, wherein the gate dielectric has a portion over the insulation region; and

a gate electrode on the gate dielectric.

2. The semiconductor structure of claim 1, wherein the first conductivity type is n-type and the second conductivity type is p-type.

3. The semiconductor structure of claim 1, wherein edges of the third HVW region are substantially aligned with edges of the second HVW region.

4. The semiconductor structure of claim 1, wherein the bottom of the third HVW region is lower than the bottom of the first HVW region by greater than about 10 nm.

5. The semiconductor structure of claim 1, wherein the third HVW region has an impurity concentration substantially close to an impurity concentration of the second HVW region.

6. The semiconductor structure of claim 1, wherein the third HVW region has an impurity concentration higher than an impurity concentration of the substrate by greater than about one order.

7. The semiconductor structure of claim 1, wherein the third HVW region has a portion overlapping the first HVW region, and wherein an overlapped region has a width of less than about 1 μ

m.

8. The semiconductor structure of claim 1 further comprising a fourth HVW region of the first conductivity on an opposite side of the first HVW region than the second HVW region, wherein the fourth HVW region has a same thickness as the first HVW region does, and wherein a region underlying the fourth HVW region is substantially free from the third HVW region, and wherein the gate dielectric extends over the fourth HVW region.

9. The semiconductor structure of claim 1, wherein the first and the third HVW regions are in physical contact with the substrate.

10. The semiconductor structure of claim 1 further comprising:

a fourth HVW region of the second conductivity type overlying the substrate and laterally adjoining the first HVW region, wherein the fourth HVW region is on an opposite side of the first HVW region than the second HVW region, and wherein a region over the fourth HVW region is free from the gate dielectric;

a fifth HVW region of the second conductivity type underlying the fourth HVW region, wherein a region underlying the first HVW region is substantially free from the fifth HVW region, and wherein the fifth HVW region has a bottom substantially lower than the bottom of the first HVW region.

11. The semiconductor structure of claim 1 further comprising:

a first source/drain region in the first HVW region and adjacent the insulation region; and

a second source/drain region in the second HVW region and adjacent the gate dielectric.

12. A semiconductor structure comprising:

a semiconductor substrate;

a first high-voltage well (HVW) region of a first conductivity type directly on the substrate;

a second HVW region of a second conductivity type opposite the first conductivity directly on the substrate and laterally adjoining the first HVW region, wherein the first HVW region has a first thickness substantially less than a second thickness of the second HVW region;

an insulation region in the first HVW region and spaced apart from an interface between the first and the second HVW regions;

a gate dielectric extending from over the insulation region to over the second HVW region; and

a gate electrode on the gate dielectric.

13. The semiconductor structure of claim 12, wherein the second thickness is greater than the first thickness by greater than about 0.1 nm.

14. The semiconductor structure of claim 12, wherein the second thickness is greater than the first thickness by greater than about 10 percent.

15. The semiconductor structure of claim 12 further comprising a third HVW region of the second conductivity type adjoining and on an opposite side of the first HVW region than the second HVNW region, wherein the third HVW region has the second thickness.

16. The semiconductor structure of claim 15, wherein the second and the third HVW regions are portions of a continuous HVW region encircling the first HVW region.

17. A semiconductor structure comprising:

a semiconductor substrate;

a high-voltage n-well (HVNW) region overlying the substrate;

a high-voltage p-well (HVPW) region overlying the substrate and encircling the HVNW region;

a p-type high-voltage anti-punch-through (HVNAPT) region only between the HVPW region and the substrate, wherein the HVNAPT region substantially overlaps the HVPW region, and wherein the HVNAPT region has a bottom substantially lower than a bottom of the HVNW region;

an insulation region in the HVNW region;

a gate dielectric extending from over the insulation region to over the HVPW region;

a gate electrode on the gate dielectric;

a first source/drain region in the HVNW region and adjacent the insulation region; and

a second source/drain region in the HVPW region and adjacent the gate dielectric.

18. The semiconductor structure of claim 17, wherein a bottom of the HVPW region substantially level with the bottom of the HVNW region.

19. The semiconductor structure of claim 17, wherein the bottom of the HVNAPT region is lower than the bottom of the HVNW region by greater than about 10 nm.

20. The semiconductor structure of claim 17, wherein the HVNAPT region has a p-type impurity concentration of between a p-type impurity concentration of the semiconductor substrate and a p-type impurity concentration of the HVPW.