Stack type semiconductor package and method of fabricating the same

• US 20080017968A1
• Filed: 06/20/2007
• Published: 01/24/2008
• Est. Priority Date: 07/18/2006
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Young-lyong, Yeom, Kun-dae, Choi, Young-shin
• Application Number:
  US11/812,580
• Publication Number:
  US 20080017968A1
• Time in Patent Office: Days
• US Class Current: 257/686
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/16237 the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48228 the bond pad being disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06568 the devices decreasing in size, e.g. pyramidical stack
• CPC Class Codes: H01L 2225/1023 the support being an insulating substrate
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49811 : Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/03 : all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 : Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/07802 : not being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

A stack type semiconductor package, and a method of fabricating the same are provided. The stack type semiconductor package may include a lower unit package and an upper unit package. The lower unit package may include a substrate, and a semiconductor chip on an upper surface of the substrate. A bump may be on an upper surface of the substrate, and a protecting layer, covering the semiconductor chip, may be formed. The protecting layer may include a via hole partially exposing the bump. The upper unit package may be on the protecting layer, and may include an internal connection solder ball on a lower surface of the upper unit package. The internal connection solder ball may be inserted into the via hole and connected to the bump.

Claims

1. A stack type semiconductor package comprising:

a lower unit package which includes

a substrate;

a semiconductor chip on an upper surface of the substrate;

a bump on an upper surface of the substrate; and

a protecting layer covering the semiconductor chip, and having a via hole partially exposing the bump, and

an upper unit package on the protecting layer which includes

an internal connection solder ball on a lower surface thereof, the internal connection solder ball insertable into the via hole and connected to the bump of the lower unit package.

2. The stack type semiconductor package of claim 1, wherein the bump is on a bump pad on the substrate.

3. The stack type semiconductor package of claim 1, wherein the lower unit package further includes an external connection solder ball on a lower surface of the substrate.

4. The stack type semiconductor package of claim 1, wherein the semiconductor chip is electrically connected to the substrate by a conductive wire.

5. The stack type semiconductor package of claim 1, further comprising:

another semiconductor chip on the semiconductor chip, wherein the protecting layer covers both semiconductor chips.

6. The stack type semiconductor package of claim 1, wherein the semiconductor chip is a flip chip.

7. The stack type semiconductor package of claim 1, wherein the upper unit package is a wafer level package, a flip chip package, or a wire bonding ball grid array (BGA) package.

8. The stack type semiconductor package of claim 1, wherein the protecting layer includes epoxy resin.

9. A method of fabricating a stack type semiconductor package comprising:

forming a bump on an upper surface of a substrate;

providing a semiconductor chip on the upper surface of the substrate;

forming a protecting layer covering the semiconductor chip and the bump on the substrate, having a via hole partially exposing the bump, so as to form a lower semiconductor package;

providing an upper semiconductor package on the protecting layer, wherein providing the upper semiconductor package includes inserting an internal connection solder ball on a lower surface of the upper semiconductor package and into the via hole partially exposing the bump and connected to the bump of the lower semiconductor package.

10. The method of claim 9, wherein forming the protecting layer having the via hole comprises:

forming a protecting layer covering the semiconductor chip and the bump on the substrate, and

forming the via hole using a laser.

11. The method of claim 9, wherein forming the protecting layer having the via hole comprises:

providing the substrate having the bump and the semiconductor chip thereon on a lower mold die;

providing an upper mold die having a mold pin corresponding to the bump on the substrate; and

filling a space between the substrate and the upper mold die with a molding material.

12. The method of claim 9, wherein forming the bump includes forming the bump on a bump pad on the substrate.

13. The method of claim 9, further comprising:

providing an external connection solder ball on a lower surface of the substrate of the lower semiconductor package.

14. The method of claim 9, wherein providing the semiconductor chip includes electrically connecting the semiconductor chip to the substrate by a conductive wire.

15. The method of claim 9, further comprising:

providing another semiconductor chip on the semiconductor chip, wherein the protecting layer is formed to cover both semiconductor chips.

16. The method of claim 9, wherein the semiconductor chip is a flip chip.

17. The method of claim 9, wherein the upper unit package is a wafer level package, a flip chip package, or a wire bonding BGA package.

18. The method of claim 9, wherein the protecting layer includes epoxy resin.