SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE

• US 20080017998A1
• Filed: 07/19/2006
• Published: 01/24/2008
• Est. Priority Date: 07/19/2006
• Status: Abandoned Application

• Current Assignee: HVVi Semiconductors Incorporated
• Original Assignee: HVVi Semiconductors Incorporated
• Inventors: Pavio, Jeanne S.
• Application Number:
  US11/458,566
• Publication Number:
  US 20080017998A1
• Time in Patent Office: Days
• US Class Current: 257/787
• CPC Class Codes: H01L 2224/0554 External layer
• CPC Class Codes: H01L 2224/0555 Shape
• CPC Class Codes: H01L 2224/0556 Disposition
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49111 the connectors connecting two common bonding areas, e.g. Litz or braid wires
• CPC Class Codes: H01L 2224/73257 Bump and wire connectors
• CPC Class Codes: H01L 23/4334 Auxiliary members in encapsulations H01L23/49568 takes precedence
• CPC Class Codes: H01L 23/49562 for devices being provided for in H01L29/00
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/91 : Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01072 : Hafnium [Hf]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13055 : Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15747 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/30111 : matching

Abstract

In various embodiments, semiconductor components and methods to manufacture semiconductor components are disclosed. In one embodiment, a semiconductor component includes a semiconductor die and multiple coplanar leads coupled to the semiconductor die, wherein the semiconductor die includes a power transistor and wherein the multiple leads are spaced apart from each other by a distance of about 0.1 millimeters (mm) or less. The semiconductor components further include a packaging material encapsulating the semiconductor die, wherein the packaging material is formed between the leads to electrically isolate the leads from each other. Other embodiments are described and claimed.

Claims

1. A semiconductor component, comprising:

a semiconductor die, wherein the semiconductor die comprises a power transistor;

a first lead coupled to the semiconductor die;

a second lead coupled to the semiconductor die;

a third lead coupled to the semiconductor die, wherein a major surface of the first lead is substantially coplanar to a major surface of the second lead and substantially coplanar to a major surface of the third lead; and

a packaging material encapsulating the semiconductor die, wherein the packaging material is formed between the first lead and the second lead and between the second lead and the third lead.

2. The semiconductor component of claim 1, wherein a distance between the gate lead and the source lead is less than about 0.1 millimeters (mm) and a distance between the source lead and the drain lead is less than about 0.1 millimeters (mm).

3. The semiconductor component of claim 1, wherein the first lead is a gate lead coupled to a gate electrode of the semiconductor die, the second lead is a source lead coupled to a source region of the semiconductor die, and the third lead is a drain lead coupled to a drain region of the semiconductor die and wherein at least a portion of the source lead is between at least a portion of the gate lead and at least a portion of the drain lead.

4. The semiconductor component of claim 3, further comprising:

an electrostatic discharge (ESD) protection circuit mounted on a first surface of the source lead; and

an input/output (I/O) impedance matching network mounted on the first surface of the source lead.

5. The semiconductor component of claim 3, further comprising a heat sink, wherein the packaging material is a plastic packaging material that encapsulates the semiconductor die, the second lead, a portion of the first lead, a portion of the third lead, and a portion of the heat sink, wherein the first lead, the second lead, and the third lead are electrically isolated from each other by the packaging material.

6. The semiconductor component of claim 5, wherein the semiconductor die has a first major surface and a second major surface and wherein the semiconductor die includes a first interconnect metal over the first major surface, a second interconnect metal over the first major surface, and a third interconnect metal over the second major surface.

7. The semiconductor component of claim 6, wherein the first lead is coupled to the first interconnect metal via at least one wafer bump, the second lead is coupled to the second interconnect metal via at least one wafer bump, and the third lead is coupled to the third interconnect metal via at least one wirebond.

8. The semiconductor component of claim 7, wherein the heat sink comprises copper, the first lead comprises copper, the second lead comprises copper, the third lead comprises copper, the wafer bumps comprise an electrically and thermally conductive material, and wherein the power transistor is a discrete radio frequency (RF) power transistor adapted to operate at frequencies greater than about 50 MHz and has a power output greater than about 5 watts.

9. The semiconductor component of claim 5, wherein a portion of the first lead is partially exposed external to the semiconductor component to provide electrical coupling of an external bias signal to the gate electrode from an external source, a portion of the second lead is partially exposed external to the semiconductor component to provide electrical coupling of an external bias signal to the drain region from an external source, and the heat sink is partially exposed external to the semiconductor component to provide electrical coupling of an external bias signal to the source region from an external source.

10. The semiconductor component of claim 1,

wherein the semiconductor die has a first major surface and a second major surface and wherein the semiconductor component includes a first interconnect metal over the first major surface, a second interconnect metal over the first major surface and separated from the first interconnect metal, and a third interconnect metal over the second major surface;

wherein the power transistor is a vertical power transistor having a gate coupled to the first interconnect metal, a source region coupled to the second interconnect metal, and a drain region couple to the third interconnect metal; and

wherein the first lead is a gate lead coupled to the first interconnect metal, the second lead is a source lead coupled to the second interconnect metal, and the third lead is a drain lead coupled to the third interconnect metal.

11. The semiconductor component of claim 1, wherein the semiconductor die overlies the first and second leads.

12. The semiconductor component of claim 11, further comprising a heat sink coupled to the second lead, wherein the second lead and the heat sink provide a relatively low resistance thermal path to remove heat generated by the semiconductor die.

13. The semiconductor component of claim 1, wherein the semiconductor component is devoid of wire bonds.

14. The semiconductor component of claim 1, wherein the semiconductor component is a discrete component.

15. The semiconductor component of claim 1, wherein the semiconductor component is an integrated component, wherein the semiconductor die is a first semiconductor die, and further comprising a second semiconductor die coupled to at least the second lead.

16. A method, comprising:

coupling a plurality of heat sinks to a leadframe at substantially the same time; and

coupling a plurality of semiconductor die to the leadframe after coupling the plurality of heat sinks to the leadframe, wherein at least one die of the plurality of semiconductor die comprises a power transistor.

17. The method of claim 16, wherein coupling the plurality of heat sinks to the leadframe comprises coupling the plurality of heat sinks to the leadframe at substantially the same time in a single step.

18. The method of claim 16, wherein coupling the plurality of semiconductor die comprises simultaneously coupling the plurality of semiconductor die to some, but not all of the plurality of leads of the leadframe prior to encapsulating the semiconductor die and a portion of the leadframe using a packaging material.

19. The method of claim 16, further comprising etching a conductive material to form the leadframe, wherein the plurality of leads comprise leads of a first type, leads of a second type, and leads of a third type, wherein all of the plurality of leads of the leadframe are substantially coplanar and spaced apart from each other, and wherein the leadframe comprises tie bars to couple the plurality of leads to each other.

20. The method of claim 19, further comprising encapsulating all of the plurality of semiconductor die and a portion of the leadframe using a molding compound to form a unitary structure comprising a plurality of semiconductor components, wherein the molding compound is formed between the leads of the first type and the leads of the second type and formed between the leads of the second type and the leads of the third type to electrically isolate the plurality of leads from each other.

21. The method of claim 19, further comprising singulating the unitary structure into individual semiconductor components using sawing or laser cutting, wherein each individual packaging component includes at least one semiconductor die and wherein each die of the plurality of semiconductor die comprises a radio frequency (RF) power transistor.

22. The method of claim 19, further comprising forming wirebonds to connect the leads of the third type to bond pads on each of the plurality of semiconductor die and wherein each die of the plurality of semiconductor die comprise a radio frequency (RF) vertical power transistor.

23. A method to manufacture a plurality of semiconductor components, comprising:

attaching a plurality of semiconductor die to a leadframe, wherein at least one die of the plurality of semiconductor die comprises a power transistor;

encapsulating all of the plurality of semiconductor die and a portion of the leadframe using a packaging material to form a unitary structure comprising a plurality of semiconductor components; and

singulating the unitary structure into individual semiconductor components.

24. The method of claim 23, further comprising attaching a plurality of heat sinks to some, but not all of the leads of the leadframe in a batch operation prior to attaching the plurality of semiconductor die to the leadframe, wherein each individual semiconductor component comprises at least one semiconductor die and wherein each of the plurality of semiconductor die comprises a vertical power transistor wherein electrical current flows essentially vertically through the power transistor from a source region of the power transistor to a drain region of the power transistor.

25. The method of claim 24, further comprising etching a metal substrate to form the leadframe, wherein the leadframe comprises a plurality of substantially coplanar, spaced apart leads and a plurality of support structures to couple the plurality of leads to each other during packaging of the plurality of semiconductor components and wherein the singulating the unitary structure includes cutting the support structures to separate the plurality of leads from each other.

26. The method of claim 25, wherein the plurality of leads comprise gate leads, source leads, and drain leads and wherein attaching the plurality of heat sinks comprises attaching the plurality of heat sinks to a first major surface of the source leads of the leadframe and wherein attaching the plurality of semiconductor die to the leadframe comprises attaching the plurality of semiconductor die to a second major surface of the source leads of the leadframe and to a first major surface of the gate leads of the leadframe.

27. The method of claim 26, wherein each individual semiconductor component includes at least one gate lead, at least one source lead, at least one drain lead, at least one heat sink and at least one semiconductor die, wherein for each individual semiconductor component:

a portion of the heat sink is exposed external to the semiconductor component, a portion of the gate lead is exposed external to the semiconductor component, and a portion of the drain lead is exposed external to the semiconductor component and the at least one heat sink of each individual semiconductor component is attached to the first major surface of the at least one source lead, a first portion of the at least one semiconductor die is attached to the second major surface of the at least one source lead, a second portion of the at least one semiconductor die is attached to a first major surface of the at least one gate lead.

28. The method of claim 26, wherein the gate and drain leads are substantially the same size and wherein the source leads are larger than the gate and drain leads and further comprising bending the gate leads and the drain leads prior to the encapsulating.

29. The method of claim 24, further comprising performing a stamping operation to form the plurality of heat sinks, wherein the stamping operation comprises stamping an electrically and thermally conductive material to form the plurality of heart sinks and wherein stamping includes forming a burr on a portion of each of the plurality of heat sinks to provide a mold lock to increase pull-out resistance of the plurality of heat sinks after the plurality of heat sinks are molded into the packaging material.

30. The method of claim 24, wherein attaching a plurality of semiconductor die to a leadframe comprises attaching the plurality of semiconductor die to a leadframe at substantially the same time and wherein attaching a plurality of heat sinks to the leadframe comprises brazing the heat sinks to the leadframe using a material comprising copper or silver.

31. The method of claim 24, further comprising plating the leadframe using a conductive material after the attaching of the plurality of heat sinks to the leadframe and prior to the attaching of the plurality of semiconductor die to the leadframe.