Configurable IC's With Configurable Logic Resources That Have Asymmetric Inputs And/Or Outputs

• US 20080018359A1
• Filed: 07/09/2007
• Published: 01/24/2008
• Est. Priority Date: 11/08/2004
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Brad Hutchings, Herman Schmit, Jason Redgrave, Randy Huang, Steve Teig
• Inventors: Huang, Randy, Teig, Steven, Redgrave, Jason, Hutchings, Brad, Schmit, Herman
• Granted Patent: US 7,518,402 B2
• Time in Patent Office: Days
• US Class Current: 326/41
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 25/065 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/11803 using field effect technology
• CPC Class Codes: H01L 27/11898 Input and output buffer/driver structures
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17796 for physical disposition of blocks

Abstract

Some embodiments provide a configurable IC that includes several configurable tiles. The configurable tiles include several interior tiles within the interior of an arrangement of configurable tiles. The arrangement has several sides that define the exterior boundary of the arrangement. In some embodiments, each configurable interior tile includes a set of configurable logic circuits, a set of configurable input-select circuits for selecting inputs to the configurable logic circuits, and a set of configurable routing interconnect circuits for routing signals between the configurable logic circuits. The set of configurable input-select circuits in each interior tile has a set of inputs that are supplied by a set of asymmetric locations in the configurable IC. Any distance between any input-select circuit in any interior tile and any boundary-defining side of the tile arrangement is greater than any distance between any particular input-select circuit in any interior tile and any circuit that provides an input to the particular input-select circuit. Also, in some embodiments, each configurable interior tile includes a set of configurable logic circuits and a set of configurable routing interconnect circuits for routing signals between the configurable logic circuits. The set of configurable logic circuits in each interior tile has a set of outputs that are supplied to a set of asymmetric locations in the configurable IC. Any distance between any logic circuit in any interior tile and any boundary-defining side of the tile arrangement is greater than any distance between any particular logic circuit in any interior tile and any circuit that receives an output of the particular logic circuit. In some embodiments, the set of asymmetric locations is a set of locations that includes at least one location that has no symmetrical relationship with any other location in the set. In some embodiments, each input-select circuit has at least one output that is supplied to one configurable logic circuit.

Claims

1-19. -19. (canceled)

20. A configurable IC comprising a plurality of configurable tiles, said configurable tiles comprising a plurality of interior tiles within the interior of an arrangement of configurable tiles, said arrangement having a plurality of sides that define the exterior boundary of the arrangement, wherein each of said plurality of interior tiles comprises:

a) a set of configurable logic circuits;

b) a set of configurable input-select circuits for selecting inputs to the configurable logic circuits, each of the set of configurable input-select circuits comprising a set of inputs that are supplied from a set of asymmetric locations in the configurable IC, and wherein a distance from each input-select circuit to a farthest boundary side from said input-select circuit is greater than a distance from said input-select circuit to a farthest of its corresponding asymmetric locations.

c) a set of configurable routing interconnect circuits for routing signals between the configurable logic circuits.

21. A configurable IC comprising:

a) an arrangement of configurable tiles, wherein said arrangement comprises a plurality of sides that define an exterior boundary of the arrangement;

b) a plurality of configurable tiles, wherein said configurable tiles comprise a plurality of interior tiles within an interior of said arrangement of configurable tiles wherein each of said plurality of interior tiles is connected to a set of tiles in a set of asymmetric locations, wherein said set of asymmetric locations has a set of relative displacements that are identical for each of said plurality of interior tiles, and wherein, for each tile in said plurality of interior tiles, said set of asymmetric locations are within said plurality of sides that define the exterior boundary.