ELECTRONIC DEVICE INCLUDING A MEMORY ARRAY AND CONDUCTIVE LINES

• US 20080019178A1
• Filed: 08/06/2007
• Published: 01/24/2008
• Est. Priority Date: 07/25/2005
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Hong, Cheong, Chindalore, Gowrishankar, Yater, Jane
• Granted Patent: US 7,471,560 B2
• Time in Patent Office: Days
• US Class Current: 365/185.05
• CPC Class Codes: G11C 16/10 Programming or data input circuits

Abstract

An electronic circuit can include a first memory cell and a second memory cell. In one embodiment, source/drain regions of the first and second memory cells can be electrically connected to each other. The source/drain regions may electrically float regardless of direction in which carriers flow through channel regions of the memory cells. In another embodiment, the first memory cell can be electrically connected to a first gate line, and the second memory cell can be electrically connected to a greater number of gate lines as compared to the first memory cell. In another aspect, the first and second memory cells are connected to the same bit line. Such bit line can electrically float when programming or reading the first memory cell or the second memory cell or any combination thereof.

Claims

1. An electronic device comprising:

a first bit line;

a second bit line;

a first memory cell having a first source/drain region and a second source/drain region, wherein the first source/drain region of the first memory cell is electrically connected to the first bit line; and

a second memory cell having a first source/drain region and a second source/drain region, wherein;

the first source/drain region of the second memory cell is electrically connected to the second bit line; and

the second source/drain region of the second memory cell is electrically connected to the second source/drain region of the first memory cell; and

a control module coupled to the first and second bit lines, wherein the electronic device is configured such that carriers can flow (1) from the first bit line to the second bit line via the second source/drain regions of the first and second memory cells or (2) from the second bit line to the first bit line via the second source/drain regions of the first and second memory cells.

2. The electronic device of claim 1, wherein each of the first and second memory cells comprises a nonvolatile memory cell.

3. The electronic device of claim 2, wherein each of the first and second memory cell comprises discontinuous storage elements.

4. The electronic device of claim 1, further comprising:

a third bit line;

a first set of other memory cells, wherein;

each memory cell within the first set of memory cells has a first source/drain region and a second source/drain region;

the first source/drain region of the each memory cell within the first set of memory cells is electrically connected to the first bit line; and

the second source/drain region of the each memory cell within the first set of memory cells is electrically connected to the third bit line; and

a second set of other memory cells, wherein;

each memory cell within the second set of memory cells has a first source/drain region and a second source/drain region;

the first source/drain region of the each memory cell within the second set of memory cells is electrically connected to the second bit line; and

the second source/drain region of the each memory cell within the first and second set of memory cells is electrically connected to the third bit line,

5. The electronic device of claim 4, wherein the third bit line is only electrically connected to the first memory cell, the second memory cell, the first set of memory cells, and the second set of memory cells.

6. The electronic device of claim 1, wherein:

the first memory cell is configured to store up to a first number of bits; and

the second memory cell is configured to store up to a second number of bits that is different from the first number of bits.

7. An electronic device comprising:

a plurality of gate lines including a first gate line;

a first memory cell electrically connected to the first gate line; and

a second memory cell electrically connected to a greater number of gate lines within the plurality of gate lines, as compared to the first memory cell.

8. The electronic device of claim 7, wherein the first and second memory cells are electrically connected to each other.

9. The electronic device of claim 7, wherein:

the first memory cell is not electrically connected to any gate line other than the first gate line; and

the second memory cell is electrically connected to a second gate line and a third gate line, wherein the plurality of gate lines includes the second and third gate lines.

10. The electronic device of claim 9, further comprising:

a first bit line electrically connected to the first memory cell;

a second bit line electrically connected to the second memory cell; and

a third bit line electrically connected to the first and second memory cells.

11. The electronic device of claim 10, wherein the first gate line and the first and second bit lines are oriented in a first orientation, wherein the first orientation is a row or a column.

12. The electronic device of claim 10, wherein all bit lines and all gate lines electrically connected to the first memory cell or the second memory cell, except for one bit line or one gate line, are oriented in a first orientation, wherein the first orientation is a row or a column.

13. The electronic device of claim 7, wherein each of the first and second memory cells comprises discontinuous storage elements.