SEMICONDUCTOR MEMORY DEVICE AND CONTROL METHOD OF THE SAME

• US 20080019182A1
• Filed: 07/16/2007
• Published: 01/24/2008
• Est. Priority Date: 07/20/2006
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Yanagidaira, Kosuke, Hara, Takahiko, Fukuda, Koichi
• Granted Patent: US 7,532,520 B2
• Time in Patent Office: Days
• US Class Current: 365/185.19
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: G11C 8/10 Decoders

Abstract

A semiconductor memory device includes a memory cell array, a voltage generating circuit, a memory circuit which stores a reference pulse number of an erase voltage of the memory cell array and a parameter, and a control circuit which controls, when a pulse number of the erase voltage exceeds the reference pulse number of the erase voltage, the voltage generating circuit in a manner to increase at least an erase verify level in accordance with the parameter.

Claims

1. A semiconductor memory device comprising:

a memory cell array;

a voltage generating circuit;

a memory circuit which stores a reference pulse number of an erase voltage of the memory cell array and a parameter; and

a control circuit which controls, when a pulse number of the erase voltage exceeds the reference pulse number of the erase voltage, the voltage generating circuit in a manner to increase at least an erase verify level in accordance with the parameter.

2. The device according to claim 1, further comprising:

a plurality of parameter registers in which the reference pulse number and the parameter, which are read out, are set.

3. The device according to claim 1, further comprising:

a plurality of cache memories into which the reference pulse number and the parameter are read out batchwise from the memory circuit.

4. The device according to claim 1, wherein the control circuit controls, when the pulse number of the erase voltage exceeds the reference pulse number of the erase voltage, the voltage generating circuit in a manner to increase a program verify level, a read level and an intermediate potential level in accordance with the parameter.

5. The device according to claim 1, wherein the reference pulse number of the erase voltage and the parameter are stored in association with each of erase units or each of read units of the memory cell array.

6. The device according to claim 1, wherein the memory circuit stores a sense-time voltage and a threshold voltage bottom shift amount, and

the device further comprises an arithmetic circuit which determines the parameter on the basis of the reference pulse number, the sense-time voltage and the plurality of threshold voltage bottom shift amount.

7. The device according to claim 6, wherein the arithmetic circuit comprises a deterioration information detection circuit which detects deterioration information on the basis of the parameter and the reference pulse number.

8. The device according to claim 7, wherein the arithmetic circuit further comprises a shift amount determination circuit which determines a shift amount on the basis of the deterioration information, the sense-time voltage and the threshold voltage bottom shift amount.

9. The device according to claim 1, wherein the memory circuit is a first page composed of a plurality of memory cells which have control electrodes commonly connected to a word line, and

the first page comprises a first data area and a first redundant area which includes a first error correcting code area and stores the parameter and the reference pulse number.

10. The device according to claim 9, wherein the device is capable of storing multi-bit data in one memory cell disposed in the memory cell array,

the memory circuit is a second page composed of a plurality of memory cells which have control electrodes commonly connected to a word line, and

the second page comprises a second data area and a second redundant area which includes a second error correcting code area and stores the parameter and the reference pulse number, a ratio of occupation of the second error correcting code area in the second redundant area being set to be greater than a ratio of occupation of the first error correcting code area in the first redundant area.

11. The device according to claim 6, wherein the device is a multilevel NAND flash memory.

12. A control method of a semiconductor memory device including a memory cell array, a voltage generating circuit, a memory circuit which stores a reference pulse number of an erase voltage of the memory cell array and a parameter, and a control circuit which controls the voltage generating circuit, the method comprising:

causing the control circuit to check whether a pulse number of the erase voltage exceeds the reference pulse number of the erase voltage, thereby detecting deterioration information of the memory cell array;

changing, if the pulse number of the erase voltage exceeds the reference pulse number of the erase voltage, the parameter in a manner to increase at least an erase verify level; and

controlling the voltage generating circuit in a manner to apply the erase voltage to the memory cell array by using the changed parameter, and executing an erase operation.

13. The control method of a semiconductor memory device, according to claim 12, further comprising:

causing the control circuit to check, after the erase operation, whether the parameter is changed or not, thereby detecting the deterioration information of the memory cell array; and

executing, in a case where the parameter is changed, a read operation for read from the memory cell array by using the parameter that is changed in a manner to increase a read level at a time of the read operation.

14. The control method of a semiconductor memory device, according to claim 12, further comprising:

causing the control circuit to check, after the erase operation, whether the parameter is changed or not, thereby detecting the deterioration information of the memory cell array; and

executing, in a case where the parameter is changed, a write operation for write in the memory cell array by using the parameter that is changed in a manner to increase a program verify level at a time of the write operation.

15. The control method of a semiconductor memory device, according to claim 12, wherein the device is capable of storing multi-bit data in one memory cell disposed in the memory cell array,

the memory circuit stores a plurality of reference pulse numbers, a plurality of sense-time voltages and a plurality of threshold voltage bottom shift amounts,

the device further comprises an arithmetic circuit which determines the parameter on the basis of the plurality of reference pulse numbers, the plurality of sense-time voltages and the plurality of threshold voltage bottom shift amounts, the arithmetic circuit comprising a deterioration information detection circuit which detects deterioration information on the basis of the parameter and the plurality of reference pulse numbers, and a shift amount determination circuit which determines a shift amount on the basis of the deterioration information, the plurality of sense-time voltages and the plurality of threshold voltage bottom shift amounts,

the deterioration information detection circuit executes a first function to detect the deterioration information on the basis of the parameter and the plurality of reference pulse numbers,

the shift amount determination circuit executes, in a case where adjustment of a threshold voltage distribution is determined to be necessary on the basis of the detected deterioration information, a second function to calculate a shift amount on the basis of the deterioration information, the sense-time voltages and the bottom shift amounts, thus changing the parameter in a manner to increase the erase verify level voltage;

and

the control circuit controls the voltage generating circuit on the basis of the changed parameter, and executes the erase operation.

16. The control method of a semiconductor memory device, according to claim 15, wherein the control circuit checks, after the erase operation, whether the parameter is changed or not, thereby detecting the deterioration information of the memory cell array,

the shift amount determination circuit executes, in a case where the adjustment of the threshold voltage distribution is determined to be necessary on the basis of the detected deterioration information, the second function to calculate a plurality of shift amounts, with respect to a plurality of threshold voltage distributions, on the basis of the deterioration information, the plurality of sense-time voltages and the plurality of bottom shift amounts, thus changing the parameter in a manner to increase values of a plurality of discrimination level voltages, and

the control circuit controls the voltage generating circuit on the basis of the changed parameter, and executes a read operation.

17. The control method of a semiconductor memory device, according to claim 15, wherein the control circuit checks, after the erase operation, whether the parameter is changed or not, thereby detecting the deterioration information of the memory cell array,

the shift amount determination circuit executes, in a case where the adjustment of the threshold voltage distribution is determined to be necessary on the basis of the detected deterioration information, the second function to calculate a plurality of shift amounts, with respect to a plurality of threshold voltage distributions, on the basis of the deterioration information, a plurality of program verify level voltages and the plurality of bottom shift amounts, thus changing the parameter in a manner to increase the plurality of program verify level voltages, and

the control circuit controls the voltage generating circuit on the basis of the changed parameter, and executes a write operation.