Memory device and method for verifying information stored in memory cells

• US 20080019187A1
• Filed: 07/19/2006
• Published: 01/24/2008
• Est. Priority Date: 07/19/2006
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Qimonda AG (Infineon Technologies AG)
• Inventors: Kux, Andreas, Richter, Detlev
• Granted Patent: US 7,457,144 B2
• Time in Patent Office: Days
• US Class Current: 365/185.22
• CPC Class Codes: G11C 16/344 Arrangements for verifying correct erasure or for detecting overerased cells
• CPC Class Codes: G11C 16/3445 Circuits or methods to verify correct erasure of nonvolatile memory cells

Abstract

A memory device comprises a plurality of first and second non-volatile memory cells arranged as an array. Each memory cell stores information. The memory device further comprises an access unit coupled to the array. The access unit stores information in the plurality of first and second non-volatile memory cells. The memory device further comprises a verifying unit coupled to the array. The verifying unit verifies the information stored in a group of the first and second memory cells by verifying only a subset of the group. The subset comprises at least one of the second memory cells.

Claims

1. A memory device, comprising:

a plurality of non-volatile memory cells arranged in an array, the plurality of non-volatile memory cells including first and second memory cells, each memory cell storing information;

an access unit coupled to the array, the access unit causing information to be stored in the plurality of non-volatile memory cells; and

a verifying unit coupled to the array, the verifying unit verifying the information stored in a group of the first and second memory cells by verifying only a subset of the group, the subset comprising at least one of the second memory cells.

2. The memory device according to claim 1, wherein the information is more difficult to store in one of the second memory cells than in one of the first memory cells.

3. The memory device according to claim 1, wherein the second memory cells are located in an area of the array that is located adjacent to irregularities of a structure of the array.

4. The memory device according claim 1, further comprising:

a plurality of wordlines coupled to the access unit; and

a plurality of bitlines coupled to the access unit, each bitline comprising at least one bitline contact;

wherein each memory cell of the plurality of first and second memory cells is coupled to one of the plurality of wordlines and to a first and to a second bitline of the plurality of bitlines.

5. The memory device according to claim 4, wherein the second memory cells are coupled to a same wordline.

6. The memory device according to claim 4, further comprising a separation area located between groups of bitlines, wherein the second memory cells are coupled to a same bitline located adjacent to the separation area.

7. The memory device according to claim 1, wherein the subset comprises all second memory cells of the group.

8. The memory device according to claim 1, wherein the verifying unit verifies the information of the subset against a first verify level that depends on a magnitude of the subset.

9. The memory device according to claim 8, wherein the verifying unit verifies the information of one of the memory cells against the first verify level or against a second verify level, wherein the verifying unit verifies each memory cell of a further subset, including said subset, or of the group against the second verify level, the first verify level being less than the second verify level in order to verify a first information value, the second verify level being less than the first verify level in order to verify a second information value.

10. The memory device according to claim 1, wherein the information stored in the memory cells of the subset is scrambled or transformed.

11. A memory device, comprising:

a plurality of non-volatile memory cells arranged in an array, each memory cell storing at least one bit of a plurality of first and second bits, each bit representing a binary value;

an access unit coupled to the array, the access unit altering the binary values of the bits stored in the plurality of non-volatile memory cells, wherein the binary value represented by the second bit is more difficult to alter due to a structure of the array or the access unit; and

a verifying unit coupled to the array, the verifying unit verifying the binary values of a group of the first and the second bits by verifying only a subset of the group, the subset comprising at least one of the second bits.

12. The memory device according to claim 11, wherein the second bits are stored in areas of the memory cells located adjacent to irregularities of the structure of the array.

13. The memory device according to claim 11, further comprising:

a plurality of wordlines coupled to the access unit;

a plurality of bitlines coupled to the access unit, the bitlines arranged in groups, each bitline comprising at least one bitline contact; and

separation areas located between two groups of bitlines;

wherein each memory cell is coupled to one of the plurality of wordlines and to a first and a second bitline of a same group of bitlines.

14. The memory device according to claim 13, wherein the second bits are stored in memory cells coupled to a same wordline located adjacent to the bitline contacts of the bitlines.

15. The memory device according to claim 13, wherein each memory cell stores a left bit and a right bit in a charge trapping layer, the left bit being stored in a first area of the memory cell located adjacent to the first bitline, the right bit being stored in a second area of the memory cell located adjacent to the second bitline.

16. The memory device according to claim 15, wherein the second bits comprise the left bits of the memory cells coupled to a same first bitline that is located adjacent to one of the separation areas.

17. The memory device according to claim 15, wherein the second bits comprise the right bits of the memory cells coupled to a same second bitline that is located adjacent to one of the separation areas.

18. The memory device according to claim 11, wherein the subset comprises all second bits of the group.

19. The memory device according to claim 11, wherein the verifying unit verifies a first binary value of the subset against a first verify level and verifies a second binary value of the subset against a second verify level, the first verify level and second verify level depending on the magnitude of the subset.

20. The memory device according to claim 19, wherein the verifying unit verifies the first binary value of a further subset, comprising said subset, or of the group against a third verify level, and the verifying unit verifies the second binary value of the further subset, comprising said subset, or of the group against a fourth verify level, the first verify level being less than the third verify level, the second verify level being larger than the fourth verify level.

21. A method for verifying information stored in a plurality of first and second non-volatile memory cells arranged as an array, each memory cell of the plurality of first and second memory cells being coupled to one of a plurality of wordlines and to a first and to a second bitline of a plurality of bitlines, each memory cell storing information, the method comprising:

storing information in the plurality of first and second non-volatile memory cells; and

verifying the information stored in a group of the first and second memory cells by verifying only a subset of the group, the subset comprising at least one of the second memory cells.

22. The method according to claim 21, wherein the information is more difficult to store in one of the second memory cells than in one of the first memory cells.

23. The method according to claim 21, wherein the second memory cells are located in an area of the array that is located adjacent to structure irregularities of the array.

24. The method according to claim 21, wherein the verifying step comprises verifying the information of each memory cell of the subset against a first verify level that is set in dependency on the magnitude of the subset.

25. The method according to claim 24, further comprising an additional verifying step that comprises verifying the information of each memory cell of a further subset, including said subset, or of the group against a second verify level, the first verify level being less than the second verify level in order to verify a first information value, the second verify level being less than the first verify level in order to verify a second information value.

26. The method according to claim 25, wherein the subset comprises a fraction of all second memory cells and the further subset comprises all second memory cells.

27. The memory according to claim 21, wherein the data stored in the memory cells of the subset is scrambled or transformed before performing verifying.

28. A method for verifying information stored in a plurality of non-volatile memory cells arranged as an array, each memory cell storing at least one bit of a plurality of first and second bits, the bit representing a binary value, each memory cell of the plurality of memory cells being coupled to one of a plurality of wordlines and to a first and to a second bitline of a plurality of bitlines, the method comprising:

altering the binary values of a first group of the plurality of first and second bits, wherein the binary value of the second bit is more difficult to alter due to a structure of the array; and

verifying the binary value of a second group by verifying only a subset of the second group, the subset comprising at least one of the second bits.

29. The method according to claim 28, wherein the second bits of the second group are stored in memory cells located in an area of the array that is located adjacent to structure irregularities of the array.

30. The method according to claim 28, wherein each memory cell stores a left bit and a right bit, the left bit being stored in a first area of the memory cell located adjacent to the first bitline, the right bit being stored in a second area of the memory cell located adjacent to the second bitline, the subset comprising the left bits of memory cells coupled to a same first bitline adjacent to the structure irregularities of the array.

31. The method according to claim 28, wherein each memory cell stores a left bit and a right bit, the left bit being stored in a first area of the memory cell located adjacent to the first bitline, the right bit being stored in a second area of the memory cell located adjacent to the second bitline, the subset comprising the right bits of memory cells coupled to a same second bitline adjacent to the structure irregularities of the array.

32. The method according to claim 28, wherein the bit is designated by a characteristic of the memory cell and the verifying step comprises verifying a first binary value of each bit of the subset against a first verify level or the verifying step comprises verifying a second binary value of each bit of the subset against a second verify level, the first verify level and second verify level are set in dependency on the magnitude of the subset.