Memory and multi-state sense amplifier thereof

• US 20080019192A1
• Filed: 05/07/2007
• Published: 01/24/2008
• Est. Priority Date: 07/20/2006
• Status: Active Grant

• Current Assignee: Industrial Technology Research Institute
• Original Assignee: Industrial Technology Research Institute
• Inventors: Su, Keng-Li, Wang, Min-Chuan, Chang, Chia-Pao, Lin, Ching-Sheng
• Granted Patent: US 7,539,068 B2
• Time in Patent Office: Days
• US Class Current: 365/189.06
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2207/063 Current sense amplifiers
• CPC Class Codes: G11C 2211/5634 Reference cells
• CPC Class Codes: G11C 2211/5645 Multilevel memory with current-mirror arrangements
• CPC Class Codes: G11C 7/06 Sense amplifiers; Associated circuits , e.g. timing or triggering circuits
• CPC Class Codes: G11C 7/062 Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
• CPC Class Codes: G11C 7/14 Dummy cell management; Sense reference voltage generators

Abstract

The invention provides a multi-state sense amplifier, coupled to at least one memory cell and a plurality of reference cells. The source follower, coupled between a first node and the output terminal of the memory cell, clamps the voltage drop across the memory cell to generate a memory cell current flowing through the first node. The source follower circuit, coupled between a plurality of second nodes and the output terminals of the reference cells, clamps the voltage drops across the reference cells to generate a plurality of reference currents respectively flowing through the second nodes. The current mirror circuit, coupled to the first node and the second nodes, duplicates the memory cell current of the first node to affect the reference currents on the second nodes, thereby generating a memory cell voltage on the first node and a plurality of reference voltages on the second nodes.

Claims

1. A multi-state sense amplifier, coupled to at least one memory cell and a plurality of reference cells, comprising:

a source follower, coupled between a first node and the output terminal of the memory cell, clamping the voltage drop across the memory cell to generate a memory cell current flowing through the first node;

a source follower circuit, coupled between a plurality of second nodes and the output terminals of the reference cells, clamping the voltage drops across the reference cells to generate a plurality of reference currents respectively flowing through the second nodes; and

a current mirror circuit, coupled to the first node and the second nodes, duplicating the memory cell current of the first node to affect the reference currents on the second nodes, thereby generating a memory cell voltage on the first node and a plurality of reference voltages on the second nodes.

2. The multi-state sense amplifier as claimed in claim 1, wherein the resistance of the memory cell is changeable, the level of the memory cell current is determined according to the resistance of the memory cell, and the levels of the reference currents are respectively determined according to the resistances of the reference cells.

3. The multi-state sense amplifier as claimed in claim 1, wherein the relative level between the memory cell voltage and the reference voltages reflects the relative level between the resistance of the memory cell and the resistances of the reference cells.

4. The multi-state sense amplifier as claimed in claim 1, wherein the multi-state sense amplifier further comprises a pre-charge circuit, coupled to the first node and the second nodes, coupling the first node and the second nodes according to a pre-charge signal to make the reference voltages identical to the memory cell voltage before the memory cell is read.

5. The multi-state sense amplifier as claimed in claim 1, wherein the multi-state sense amplifier further comprises a voltage clamp circuit, coupled to the second nodes, keeping the voltages of the second nodes at a first clamp voltage according to a voltage clamp signal when the memory cell is coupled to the multi-state sense amplifier.

6. The multi-state sense amplifier as claimed in claim 1, wherein the current mirror circuit comprises:

a first transistor, having a source coupled to a voltage source and a gate and a drain coupled to the first node, and generating the memory cell voltage on the first node; and

a plurality of second transistors, having sources coupled to the voltage source, gates coupled to the first node, and drains respectively coupled to one of the second nodes, and generating the reference voltages on the second nodes.

7. The multi-state sense amplifier as claimed in claim 1, wherein the source follower comprises a third transistor, having a gate coupled to a second clamp voltage, a drain coupled to the first node, and a source coupled to the output terminal of the memory cell, and clamping the voltage drop across the memory cell, and the source follower circuit comprises a plurality of fourth transistors, having gates coupled to the second clamp voltage, drains respectively coupled to one of the second nodes, and sources coupled to one of the output terminals of the reference cells.

8. The multi-state sense amplifier as claimed in claim 4, wherein the pre-charge circuit comprises a plurality of first switches, respectively coupled between the first node and one of the second nodes, and the pre-charge signal turns on the first switches to couple the first node and the second nodes.

9. The multi-state sense amplifier as claimed in claim 5, wherein the voltage clamp circuit comprises a plurality of second switches, respectively coupled between the first clamp voltage and one of the second nodes, and the voltage clamp signal turns on the second switches to couple the second nodes to the first clamp voltage.

10. The multi-state sense amplifier as claimed in claim 1, wherein the memory cell is a Magnetic Random Access Memory (MRAM) cell having 2^N steady resistance states, each reference cell having a different resistance, and the number of the reference cells is (2^N−

1), wherein N is a number of the bits stored in the memory cell.

11. The multi-state sense amplifier as claimed in claim 1, wherein the memory cell is a memory cell having 2^N steady resistance states, wherein N is a number of the bits stored in the memory cell.

12. The multi-state sense amplifier as claimed in claim 1, wherein each of the reference cells is formed by coupling two resistors in parallel between the output terminals of the reference cells and a ground.

13. The multi-state sense amplifier as claimed in claim 1, wherein each of the reference cells is formed by coupling a plurality of resistors between the output terminals of the reference cells and a ground.

14. The multi-state sense amplifier as claimed in claim 1, wherein the multi-state sense amplifier is coupled to a plurality of comparators, each of which compares the memory cell voltage with one of the reference voltages to obtain a plurality of comparison result signals.

15. The multi-state sense amplifier as claimed in claim 14, wherein the comparators are coupled to a decoder decoding the comparison result signals to obtain data bits stored in the memory cell.

16. A memory, comprising:

at least one memory cell, having changeable resistance;

a plurality of reference cells, having different resistance;

a multi-state sense amplifier, coupled to the memory cell and the reference cells, generating a memory cell voltage and a plurality of reference voltages according to the resistance of the memory cell and the resistance of the reference cells;

a comparator, coupled to the multi-state sense amplifier, comparing the memory cell voltage and the reference voltages to obtain a comparison result signal; and

a decoder, coupled to the comparator, decoding the comparison result signals to obtain N bits of data stored in the memory cell.

17. The memory as claimed in claim 16, wherein the multi-state sense amplifier comprises a source follower coupled between a first node and the output terminal of the memory cell, a source follower circuit coupled between a plurality of second nodes and the output terminals of the reference cells, and a current mirror circuit coupled to the first node and the second nodes.

18. The memory as claimed in claim 17, wherein the source follower clamps the voltage drop across the memory cell to generate a memory cell current flowing through the first node, the source follower circuit clamps the voltage drops across the reference cells to generate a plurality of reference currents respectively flowing through the second nodes, the current mirror circuit duplicates the memory cell current of the first node to affect the reference currents on the second nodes, thereby generating a memory cell voltage on the first node and a plurality of reference voltages on the second nodes.

19. The memory as claimed in claim 18, wherein the level of the memory cell current is determined according to the resistance of the memory cell, and the levels of the reference currents are respectively determined according to the resistances of the reference cells.

20. The memory as claimed in claim 16, wherein the relative level between the memory cell voltage and the reference voltages reflects the relative level between the resistance of the memory cell and the resistances of the reference cells.

21. The memory as claimed in claim 17, wherein the multi-state sense amplifier further comprises a pre-charge circuit, coupled to the first node and the second nodes, coupling the first node and the second nodes according to a pre-charge signal to make the reference voltages identical to the memory cell voltage before the memory cell is read.

22. The memory as claimed in claim 17, wherein the multi-state sense amplifier further comprises a voltage clamp circuit, coupled to the second nodes, keeping the voltages of the second nodes at a first clamp voltage according to a voltage clamp signal when the memory cell is coupled to the multi-state sense amplifier.

23. The memory as claimed in claim 18, wherein the current mirror circuit comprises:

a first transistor, having a source coupled to a voltage source and a gate and a drain coupled to the first node, and generating the memory cell voltage on the first node; and

a plurality of second transistors, having sources coupled to the voltage source, gates coupled to the first node, and drains respectively coupled to one of the second nodes, and generating the reference voltages on the second nodes.

24. The memory as claimed in claim 18, wherein the source follower comprises a third transistor, having a gate coupled to a second clamp voltage, a drain coupled to the first node, and a source coupled to the output terminal of the memory cell, and clamping the voltage drop across the memory cell, and the source follower circuit comprises a plurality of fourth transistors, having gates coupled to the second clamp voltage, drains respectively coupled to one of the second nodes, and sources coupled to one of the output terminals of the reference cells.

25. The memory as claimed in claim 21, wherein the pre-charge circuit comprises a plurality of first switches, respectively coupled between the first node and one of the second nodes, and the pre-charge signal turns on the first switches to couple the first node and the second nodes.

26. The memory as claimed in claim 22, wherein the voltage clamp circuit comprises a plurality of second switches, respectively coupled between the first clamp voltage and one of the second nodes, and the voltage clamp signal turns on the second switches to couple the second nodes to the first clamp voltage.

27. The memory as claimed in claim 16, wherein the memory cell is a Magnetic Random Access Memory (MRAM) cell having 2^N steady resistance states, each reference cell having a different resistance, and the number of the reference cells is (2^N−

1), wherein N is a number of the bits stored in the memory cell.

28. The memory as claimed in claim 16, wherein the memory cell is a memory cell having 2^N steady resistance states, wherein N is a number of the bits stored in the memory cell.

29. The memory as claimed in claim 16, wherein each of the reference cells is formed by coupling two resistors in parallel between the output terminals of the reference cells and a ground.

30. The memory as claimed in claim 16, wherein each of the reference cells is formed by coupling a plurality of resistors between the output terminals of the reference cells and a ground.