Adaptive resource allocation for orthogonal frequency division multiple access

• US 20080019303A1
• Filed: 07/21/2006
• Published: 01/24/2008
• Est. Priority Date: 07/21/2006
• Status: Abandoned Application

• Current Assignee: Troicom Incorporated
• Original Assignee: Troicom Incorporated
• Inventors: Baek, Andrew, Cook, Thomas
• Application Number:
  US11/491,505
• Publication Number:
  US 20080019303A1
• Time in Patent Office: Days
• US Class Current: 370/328
• CPC Class Codes: H04L 5/0007 the frequencies being orthogonal, e.g. OFDM(A), DMT
• CPC Class Codes: H04L 5/0037 Inter-user or inter-terminal allocation
• CPC Class Codes: H04L 5/0058 Allocation criteria

Abstract

Disclosed is an adaptive hardware resource allocation architecture that results in power consumption reduction. The architecture incorporates a novel concept in that the system resources can be optimally configured based on estimated processing requirements for the OFDMA mobile unit. The estimation is based on data burst attributes, data burst statistics, and message types.

Claims

1. A hardware resource allocation manager for implementing dynamic resource allocation for an orthogonal frequency division multiple access transceiver, wherein the transceiver processes a frame, the frame comprising header information and data, the hardware allocation manager comprising:

means for analyzing the header information to estimate at least one of memory allocation requirements, functional block configuration requirements, and processing requirements for processing the data; and

means for adaptively allocating at least one of processing resources of a processor responsive to the processing requirements, a quantity of memory blocks available to the processor responsive to the memory allocation requirements, and configuration of functional blocks available to the processor responsive to the functional block configuration requirements.

2. A hardware allocation manager according to claim 1, further comprising:

means for observing variations in the header information over a plurality of frames; and

means for including the observed variations in estimating at least one of the memory allocation requirements, the functional block configuration requirements, and the processing requirements.

3. A hardware allocation manager according to claim 1, wherein a processor is coupled to the hardware allocation manager to provide processor feedback information, and the hardware allocation manager comprises means for including the processing feedback information in estimating at least one of the memory allocation requirements, the functional block configuration requirements, and the processing requirements.

4. A hardware allocation manager according to claim 3, wherein the processor measures an amount of time the processor takes to process the data;

and

the processor communicates the amount of time to the hardware allocation manager as the processing feedback information.

5. A hardware allocation manager according to claim 1, wherein the hardware allocation manager determines at least one of the processing resources, the quantity of memory blocks available to the processor, and the configuration of functional blocks available to the processor from:

a number of data bursts and a number of messages;

sizes of data bursts and sizes of messages; and

types of data bursts and types of messages.

6. A hardware allocation manager according to claim 1, wherein the hardware allocation manager receives a repetition coding number, a coding type, and a downlink header size from the header information to estimate at least one of the memory allocation requirements, the functional block configuration requirements, and the processing requirements.

7. A hardware allocation manager according to claim 1, wherein the header information is located in a downlink header and an uplink header.

8. A hardware allocation manager according to claim 7, wherein the hardware allocation manager receives symbol offset information, subchannel offset information, a number of symbols, a number of subchannels, and a repetition coding number from the downlink header to estimate at least one of the memory allocation requirements, the functional block configuration requirements, and the processing requirements.

9. A hardware allocation manager according to claim 7, wherein the hardware allocation manager receives symbol offset information, subchannel offset information, a number of symbols, a number of subchannels, and a repetition coding indication from the uplink header to estimate at least one of the memory allocation requirements, the functional block configuration requirements, and the processing requirements.

10. A hardware allocation manager according to claim 1, wherein the hardware allocation manager receives information located in at least one of uplink channel descriptor messages and downlink channel descriptor messages to estimate at least one of the memory allocation requirements, the functional block configuration requirements, and the processing requirements.

11. A hardware allocation manager according to claim 10, wherein the information located in at least one of the uplink channel descriptor messages and the downlink channel descriptor messages comprises:

burst modulation type; and

forward error correction type.

12. A hardware allocation manager according to claim 1, wherein said hardware allocation manager comprises:

a data pattern analyzer; and

a control signal generator.

13. A method for dynamically allocating at least one of processor resources, memory resources, and functional block resources in an orthogonal frequency division multiple access transceiver to improve power consumption, comprising:

receiving a current frame, the current frame comprising header information and data;

determining from the header information, at least one of processing requirements, memory allocation requirements, and functional block configuration requirements for processing the data of the current frame;

adjusting at least one of a processor clock speed of the transceiver responsive to the processing requirements, a quantity of memory blocks available to a processor of the transceiver responsive to the memory allocation requirements, and a configuration of functional blocks available to the processor of the transceiver responsive to the functional block configuration requirements.

14. A baseband chip for an orthogonal frequency division multiple access transceiver, comprising:

a physical layer;

a memory;

a lower MAC;

a processor; and

a hardware allocation manager, wherein

the lower MAC provides decoding of packet header information;

the hardware allocation manager is coupled to receive the decoded packet header information; and

the hardware allocation manager communicates with at least one of the memory to adaptively adjust a quantity of memory blocks available to the processor, the physical layer and the lower MAC to adaptively adjust a configuration of functional blocks available to the processor, and the processor to adaptively adjust a processor clock speed responsive to changes in data traffic loads reflected in the decoded packet header information.

15. A method for dynamically allocating at least one of processor resources, memory resources, and functional block resources in an orthogonal frequency division multiple access transceiver to improve power consumption, comprising:

receiving a series of frames, each frame comprising corresponding header information;

determining at least one of processing requirements, memory allocation requirements, and functional block configuration requirements from the corresponding header information;

monitoring how much at least one of the processing requirements, the memory allocation requirements, and the functional block configuration requirements vary over time;

adjusting at least one of a processor clock speed of the transceiver responsive to a variance of the processing requirements over time, a quantity of memory blocks available to a processor of the transceiver responsive to a variance of the memory allocation requirements over time, and a configuration of functional blocks available to the processor of the transceiver responsive a variance of the functional block configuration requirements over time.