SYSTEM AND METHOD FOR TRANSMITTING DATA ON RETURN PATH OF A CABLE TELEVISION SYSTEM

• US 20080019706A1
• Filed: 08/13/2007
• Published: 01/24/2008
• Est. Priority Date: 12/13/1999
• Status: Active Grant

• Current Assignee: II-VI Delaware, Inc. (Coherent Corp.)
• Original Assignee: Finisar Corporation (II-VI Incorporated)
• Inventors: Levinson, Frank, Sage, Gerald, Lawson, Arthur, Mostert, Willem
• Granted Patent: US 7,778,554 B2
• Time in Patent Office: Days
• US Class Current: 398/202
• CPC Class Codes: H04N 21/615 Signal processing at physical level signal processing in analog two-way television systems H04N7/173
• CPC Class Codes: H04N 21/6168 involving cable transmission, e.g. using a cable modem
• CPC Class Codes: H04N 7/17309 Transmission or handling of upstream communications
• CPC Class Codes: H04N 7/22 Adaptations for optical transmission

Abstract

An optical signal return path system includes a transmitter having a sample clock generator for generating a sample clock and an RF signal receiver for receiving and converting an analog RF data signal into a first data stream of digitized RF data samples at a rate determined by the sample clock. Supplemental channel circuitry provides a second data stream. A multiplexor receives and combines the first data stream and second data stream, and an optical transmitter converting the combined data stream into a serialized optical data signal for transmission over an optical fiber. The second data stream may contain maintenance data reflecting an operational state of the transmitter. A receiver receives the optical data signal and recovers therefrom a digital data stream and an associated first clock having an associated first clock rate. The data stream is stored in a memory device at the first clock rate. A clock generator generates a second clock having an associated second clock rate that is adjusted in accordance with a clock control signal. A control circuit reads data from the memory device at a rate corresponding to the second clock rate and generates a fullness signal that indicates whether the memory device is more full than a predefined threshold fullness level. A clock speed adjusting circuit generates the clock control signal in accordance with the fullness signal.

Claims

1. An optical signal receiver comprising:

a signal receiver configured to receive an digital input signal and recover therefrom a digital data stream and an associated first clock having an associated first clock rate;

a memory device configured to store the data stream at a rate corresponding to the first clock rate;

a clock generator configured to generate a second clock having an associated second clock rate, wherein the clock generator is configured to adjust the second clock rate in accordance with a clock control signal;

logic configured to read data from the memory device at a rate corresponding to the second clock rate and to generate a fullness signal that indicates whether the memory device is more full than a predefined threshold fullness level; and

a clock speed adjusting circuit configured to generate the clock control signal in accordance with the fullness signal.

2. The receiver of claim 1, wherein the clock generator includes a voltage controlled crystal oscillator and the clock control signal is a voltage signal.

3. An optical signal receiver comprising:

a signal receiver configured to receive an digital input signal and recovering therefrom a digital data stream and an associated first clock having an associated first clock rate, the digital data stream including a first data stream having an associated first data rate and a second data stream having an associated second data rate that is different from the first data rate;

the first data stream comprising a sequence of data frames, each data frame representing a sequence of samples of an RF signal;

a first memory device configured to store the first data stream;

a second memory device configured to store the second data stream;

a demultiplexer configured to receive the digital data stream, detect boundaries of the data frames in the first data stream and store the data frames in the first memory device, identify data in the digital data stream comprising the second data stream and store the second data stream in the second memory device;

a clock generator configured to generate a local sample clock having an associated sample clock rate;

logic circuitry configured to read data from the first memory device at a rate corresponding to the sample clock rate so as to regenerate the sequence of samples of the RF signal represented by the sequence of data frames comprising the first data stream; and

a digital to analog converter configured to convert the regenerated sequence of samples at the sample clock rate into an analog signal comprising a regenerated version of the RF signal.

4. The receiver of claim 3, wherein:

the logic circuitry is configured to generate a fullness signal that indicates whether the first memory device is more full than a predefined threshold fullness level;

the clock generator is configured to adjust the sample clock rate in accordance with a clock control signal; and

the receiver includes a clock speed adjusting circuit configured to generate the clock control signal in accordance with the fullness signal.

5. The receiver of claim 4, wherein the logic circuitry is configured to read data from the second memory device and transmit the data read from the second memory device to a digital data device.

6. The receiver of claim 5, wherein the digital data device is a data processor.

7. The receiver of claim 5, wherein the digital data device is coupled to a network router for routing data packets in the second data stream.

8. An optical signal receiver comprising:

a signal receiver configured to receive a digital input signal and recover therefrom a digital data stream and an associated first clock having an associated first clock rate, the digital data stream including first, second and third data streams, the first data stream comprising a first sequence of first data frames, each first data frame representing a sequence of samples of a first RF signal, the second data stream comprising a second sequence of second data frames, each second data frame representing a sequence of samples of a second RF signal;

a first memory device configured to store the first data stream;

a second memory device configured to store the second data stream;

a third memory device configured to store the third data stream;

a demultiplexer configured to receive the digital data stream, detect boundaries of the first data frames in the first data stream and of the second data frames in the second data stream and store the first data frames in the first memory device and the second data frames in the second memory device, identify data in the digital data stream comprising the third data stream and store the third data stream in the third memory device;

a clock generator configured to generate a local sample clock having an associated sample clock rate;

logic circuitry for simultaneously reading data from the first and second memory devices at a rate corresponding to the sample clock rate so as to regenerate the sequence of samples of the first RF signal represented by the sequence of first data frames comprising the first data stream and the sequence of samples of the second RF signal represented by the sequence of second data frames comprising the second data stream;

a first digital to analog converter configured to convert the regenerated sequence of samples of the first RF signal at the sample clock rate into an analog signal comprising a regenerated version of the first RF signal; and

a second digital to analog converter configured to convert the regenerated sequence of samples of the second RF signal at the sample clock rate into an analog signal comprising a regenerated version of the second RF signal.

9. The receiver of claim 8, wherein the logic circuitry is configured to read data from the third memory device and transmit the data read from the third memory device to a digital data device.

10. An optical signal receiver comprising:

a signal receiver configured to receive a digital input signal and recover therefrom a digital data stream and an associated first clock having an associated first clock rate, the digital data stream including a first data stream having an associated first data rate and a second data stream having an associated second data rate that is different from the first data rate;

the first data stream comprising a sequence of data frames, each data frame representing a sequence of summed samples of a plurality of RF signals, each summed sample comprising a mathematical sum of samples of a plurality of distinct RF signals;

a first memory device configured to store the first data stream;

a second memory device configured to store the second data stream;

a demultiplexer configured to receive the digital data stream, detect boundaries of the data frames in the first data stream and store the data frames in the first memory device, identify data in the digital data stream comprising the second data stream and store the second data stream in the second memory device;

a clock generator configured to generate a local sample clock having an associated sample clock rate;

logic circuitry configured to read data from the first memory device at a rate corresponding to the sample clock rate so as to regenerate the sequence of summed samples of the plurality of RF signals represented by the sequence of data frames comprising the first data stream; and

a digital to analog converter configured to convert the regenerated sequence of samples at the sample clock rate into an analog signal comprising a regenerated version of the plurality of RF signals superimposed on each other.

11. The receiver of claim 10, further including a cable modem termination system (CMTS) coupled to the digital to analog converter and configured to receive the analog signal and reconstruct therefrom digital messages encoded within each of the plurality of RF signals.

12. A method of receiving a digital input signal, comprising:

receiving the digital input signal and recovering therefrom a digital data stream and an associated first clock having an associated first clock rate;

storing the data stream in a memory device at a rate corresponding to the first clock rate;

generating a second clock having an associated second clock rate, and adjusting the second clock rate in accordance with a clock control signal;

reading data from the memory device at a rate corresponding to the second clock rate;

generating a fullness signal that indicates whether the memory device is more full than a predefined threshold fullness level; and

generating the clock control signal in accordance with the fullness signal.

13. The method of claim 12, wherein the second clock is generated using a voltage controlled crystal oscillator and the clock control signal is a voltage signal.