STORAGE CIRCUIT AND METHOD THEREFOR

• US 20080022047A1
• Filed: 10/01/2007
• Published: 01/24/2008
• Est. Priority Date: 05/19/2005
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Palmer, Jeremiah, Kenkare, Prashant, Ramaraju, Ravindraraj
• Granted Patent: US 7,525,867 B2
• Time in Patent Office: Days
• US Class Current: 711/128
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 15/00 Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores

Abstract

Storage circuits (180-183 and 280-281) may be used for low power operation while allowing fast read access. In one embodiment (e.g. circuit 100), shared complementary write bit lines (101, 102), separate read bit lines (103-106), a shared read word line (107), and separate write word lines (108-111) are used. In an alternate embodiment (e.g. circuit 200), shared complementary write bit lines (201, 202), a shared read bit line (203), separate read word lines (206-207), and separate write word lines (208-209) are used. The storage circuit may be used in a variety of contexts, such as, for example, a register file (17), a branch unit (15), an SRAM (19), other modules (20), a cache (18), a buffer (21), and/or a memory (14).

Claims

1-6. -6. (canceled)

7. A method for processing data in a data storage circuit comprising:

storing a first data value in a first storage cell having a first terminal and a second terminal;

storing a second data value in a second storage cell having a first terminal and a second terminal;

coupling a shared write bit line to each of the first storage cell and the second storage cell for selectively providing both the first data value and the second data value to the first storage cell and the second storage cell, respectively;

selectively reading only the first storage cell via a first read bit line coupled to the first storage cell; and

selectively reading only the second storage cell via a second read bit line coupled to the second storage cell.

8. The method of claim 7 further comprising:

selectively enabling reading each of the first storage cell and the second storage cell in response a common read signal via a shared read word line.

9. The method of claim 7 further comprising:

implementing the first storage cell and the second storage cell as one of a static random access memory (SRAM) cell, a register, a cache tag array memory cell, a buffer or a branch unit memory cell.

10. The method of claim 7 further comprising:

enabling a first select gate coupled to the first terminal of the first storage cell via a first write word line;

writing the first storage cell;

enabling a second select gate coupled to the second terminal of the second storage cell via a second write word line; and

writing the second storage cell.

11. The method of claim 10 further comprising:

providing a third select gate coupled to the second terminal of the first storage cell, the third select gate being controlled by the first write word line; and

providing a fourth select gate coupled to the first terminal of the second storage cell, the fourth select gate being controlled by the second write word line.

12. The method of claim 10 further comprising:

assigning the first storage cell to a first way of an associative memory; and

assigning the second storage cell to a second way of the associative memory.

13-17. -17. (canceled)

18. A method for processing data in a data storage circuit comprising:

providing a first storage cell having a first terminal and a second terminal for storing a first data value;

providing a second storage cell having a first terminal and a second terminal for storing a second data value;

coupling a shared write bit line to the first terminal of each of the first storage cell and the second storage cell for selectively providing both the first data value and the second data value to the first storage cell and the second storage cell, respectively; and

coupling a shared read bit line to each of the first storage cell and the second storage cell for selectively reading each of the first storage cell and the second storage cell.

19. The method of claim 18 further comprising:

providing a complementary bit line that is a complement of at least one of the shared write bit line or the shared read bit line to enhance operation of the first storage cell and the second storage cell.

20. The method of claim 18 further comprising:

coupling a first write word line to the first storage cell and coupling a second write word line to the second storage cell for selectively separately writing the first storage cell and the second storage cell; and

coupling a first read word line to the first storage cell and coupling a second read word line to the second storage cell for selectively separately reading the first storage cell and the second storage cell.

21. The method of claim 18 further comprising:

assigning the first storage cell to a first context or first thread in a data processing system; and

assigning the second storage cell to a second context or second thread in the data processing system.

22. A method comprising:

providing a first storage cell having a first terminal and a second terminal for storing a first data value;

providing a second storage cell having a first terminal and a second terminal for storing a second data value;

providing a shared write bit line coupled to each of the first storage cell and the second storage cell for selectively providing both the first data value and the second data value to the first storage cell and the second storage cell, respectively,

wherein the first data value and the second data value are non-concurrently writable.

23. A method as in claim 22 further comprising:

providing a first read bit line coupled to the first storage cell for selectively reading only the first storage cell; and

providing a second read bit line coupled to the second storage cell for selectively reading only the second storage cell.

24. A method as in claim 22 further comprising:

providing a shared read word line for selectively enabling reading each of the first storage cell and second storage cell in response to a shared read signal.

25. A method as in claim 22 wherein the first storage cell and the second storage cell each comprise one of a static random access memory (SRAM) cell, a register, a cache tag array memory cell, a buffer or a branch unit memory cell.

26. A method as in claim 22 further comprising:

providing a first select gate coupled to the first terminal of the first storage cell;

providing a second select gate coupled to the second terminal of the second storage cell;

providing a first write word line coupled to the first select gate, the first write word line enabling the first select gate to write the first storage cell;

providing a second write word line coupled to the second select gate, the second write word line enabling the second select gate to write the second storage cell.

27. A method as in claim 26 further comprising:

providing a third select gate coupled to the second terminal of the first storage cell, the third select gate being controlled by the first write word line; and

providing a fourth select gate coupled to the first terminal of the second storage cell, the fourth select gate being controlled by the second write word line.

28. A method as in claim 22 further comprising:

assigning the first storage cell to a first way of an associative memory and the second storage cell is assigned to a second way of the associative memory.