Information processing device

• US 20080022154A1
• Filed: 09/21/2007
• Published: 01/24/2008
• Est. Priority Date: 03/24/2005
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Endou, Shin
• Granted Patent: US 8,527,806 B2
• Time in Patent Office: Days
• US Class Current: 714/30
• CPC Class Codes: G06F 11/073 in a memory management context, e.g. virtual memory or cache management memory management G06F12/00; testing of static memory units G11C29/00
• CPC Class Codes: G06F 11/0751 Error or fault detection not based on redundancy power supply failures G06F1/30; network fault management H04L41/06
• CPC Class Codes: G06F 11/0772 Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers
• CPC Class Codes: G06F 11/1008 in individual solid state devices G06F11/1004 takes precedence

Abstract

The present invention provides an information processing device having a CPU which executes an OS and firmware, and a plurality of memory controllers which are connected to the CPU, control writing to and reading from a plurality of memory units, and perform error monitoring, wherein the plurality of memory units each connected to the plurality of memory controllers, the memory controllers sequentially read memory areas of the plurality of memory units connected to the memory controllers, and perform error area monitoring, and the firmware converts addresses recognized by the memory controllers corresponding to the error areas into logical addresses recognized by the OS, and supplies the logical addresses to the OS.

Claims

1. An information processing device, comprising:

a CPU which executes an OS and firmware; and

a plurality of memory controllers which are connected to the CPU, control writing to and reading from a plurality of memory units, and perform error monitoring, wherein the plurality of memory units each connected to the plurality of memory controllers,

the memory controllers sequentially read memory areas of the plurality of memory units connected to the memory controllers, and perform error area monitoring; and

the firmware converts addresses recognized by the memory controllers corresponding to the error areas into logical addresses recognized by the OS, and supplies the logical addresses to the OS.

2. The information processing device according to claim 1, wherein the firmware judges whether the error areas detected by the memory controllers are areas which have been detected to be error areas by previous reading and have been excluded from usable areas, and resumes reading of memory areas if the areas have been excluded.

3. The information processing device according to claim 1, wherein the firmware judges whether data in the error area is restorable, and the memory-controller detecting the error area performs rewriting of the error area if the data in the error area is restorable.

4. The information processing device according to claim 1, wherein the plurality of memory controllers each perform monitoring of the memory errors independently.

5. A memory anomaly monitoring method in an information processing device having a CPU which executes an OS and firmware, a plurality of memory controllers which are connected to the CPU, control writing to and reading from a plurality of memory units, and perform error monitoring, and the plurality of memory units each connected to the plurality of memory controllers, the method comprising the steps of:

sequential reading memory areas in the plurality of memory units connected to the memory controllers, and performing error area monitoring, by the memory controllers; and

,

converting addresses recognized by the memory controllers corresponding to the error areas into logical addresses recognized by the OS, and supplying the logical addresses to the OS, by the firmware.

6. The memory anomaly monitoring method according to claim 5, further comprising a step of degradation judgment of judging whether the error area detected by the memory controller is an area which has been detected as an error area by previous reading and has been excluded from usable areas, and resuming memory area reading if the area is previously excluded, by the firmware.

7. The memory anomaly monitoring method according to claim 5, further comprising a step of restoration judgment of judging, by the firmware, whether the data of the error area can be restored, and performing rewriting of the error data, by the memory controller which has detected the error area, if the data of the error area can be restored.