Storage system and data protection method therefor

• US 20080022163A1
• Filed: 08/11/2006
• Published: 01/24/2008
• Est. Priority Date: 06/28/2006
• Status: Active Grant

• Current Assignee: Rakuten Group, Inc.
• Original Assignee: Hitachi, Ltd.
• Inventors: Nakamura, Shuji, Tanaka, Katsuya
• Granted Patent: US 7,574,554 B2
• Time in Patent Office: Days
• US Class Current: 714/710
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 12/0866 for peripheral storage systems, e.g. disk cache
• CPC Class Codes: G06F 12/1416 by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights G06F12/1458 takes precedence
• CPC Class Codes: G06F 2212/214 Solid state disk
• CPC Class Codes: G06F 2212/262 configured as RAID
• CPC Class Codes: G06F 3/0601 Interfaces specially adapted for storage systems
• CPC Class Codes: G06F 3/0664 at device level, e.g. emulation of a storage device or system

Abstract

To detect an address error in flash memory using a different data management unit from that in a hard disk drive. In cache memory, data read/written from/to a flash memory chip is managed in units of first data lengths. A page, which is the data management unit in a flash memory chip, includes a data section of a second data length from/to which a storage controller can read/write data; and a redundant section. When writing data, the storage controller creates a protection code enabling identification of a write destination page address, divides the data in the cache memory, which is managed in units of first data lengths, into pieces so that the size of each set composed of a piece of the divided write data and its protection code will be of a second data length, and writes the respective sets in a flash memory chip in units of second data lengths.

Claims

1. A storage system comprising:

one or more flash memory modules each having one or more flash memory chips and a memory controller that controls reading/writing of data from/to the flash memory chips; and

a storage controller having cache memory that temporarily stores data read/written from/to one or more of the flash memory chips,

wherein,

in the cache memory, data read/written from/to the flash memory chips is managed in units of first data lengths;

in the flash memory modules, the data read/written from/to the flash memory chips is managed in page units;

the memory area of one page includes a memory area of a second length from/to which the storage controller can read/write data, and a memory area for a redundant section;

when writing data in a flash memory chip, the storage controller creates a protection code enabling identification of address information for a write destination page;

divides the data in the cache memory, which is managed in units of first data lengths, into pieces so that the size of each set composed of a piece of the divided write data and its protection code will be of the second data length, and writes the respective sets of the pieces of write data and protection codes in the flash memory chip in units of second data lengths; and

the storage controller compares the address information identified with the protection codes attached to the data read from the flash memory chip with the address information for the data that is intended to be read, and checks whether there is an address error or not.

2. The storage system according to claim 1, wherein the storage controller further includes a database storing relationships between the specifications of the flash memory modules and the second data lengths of the same.

3. The storage system according to claim 1,

wherein the storage areas provided by flash memory modules are structured according to RAID;

and

when an address error occurs in the data in any one of the flash memory modules, the storage controller rebuilds the data having the address error in units of the second data lengths using the data stored in the other flash memory modules belonging to the same RAID group as the flash memory module storing the data having the address error; and

overwrites the data having the address error with the rebuilt data.

4. The storage system according to claim 1, the storage system further includes hard disk drives as storage media, wherein when an address error occurs in a hard disk drive, the storage controller overwrites/corrects the data having the address error in units of the first data lengths.

5. The storage system according to claim 1, wherein any one of the protection codes includes write-time information.

6. The storage system according to claim 1, wherein any one of the protection codes includes an error detection code for protecting data of the second data length.

7. A storage system comprising:

one or more flash memory modules each having one or more flash memory chips and a memory controller that controls reading/writing of data from/to the flash memory chips; and

a storage controller having cache memory that temporarily stores data read/written from/to one or more of the flash memory chips,

wherein,

in the cache memory, data read/written from/to the flash memory chips is managed in units of first data lengths;

in the flash memory modules, the data read/written from/to the flash memory chips is managed in page units;

the memory area of one page includes a memory area of a second length from/to which the storage controller can read/write data, and a memory area for a redundant section;

the storage controller has a media identification unit that identifies the type of a storage medium connected thereto;

if a storage medium connected to the storage controller is a flash memory module, when writing data in a flash memory chip, the storage controller creates a protection code enabling identification of address information for a write destination page;

divides the data in the cache memory, which is managed in units of first data lengths, into pieces so that the size of each set composed of a piece of the divided write data and its protection code will be of the second data length, and writes the respective sets of the pieces of the write data and protection code in the flash memory chip in units of second data lengths; and

the storage controller compares the address information identified with the protection codes attached to the data read from the flash memory chip with the address information for the data that is intended to be read, and checks whether there is an address error or not.

8. The storage system according to claim 7, wherein the first data length is the sector length of a hard disk drive.

9. The storage system according to claim 7, wherein data of the first data length includes data and a protection code enabling identification of address information of a write destination hard disk drive for that data.

10. The storage system according to claim 7, wherein the storage controller further includes a database storing relationships between the specifications of the storage media and the second data lengths of the same.

11. The storage system according to claim 7,

wherein the storage areas provided by flash memory modules are structured according to RAID;

and

when an address error occurs in the data in any one of the flash memory modules, the storage controller rebuilds the data having the address error in units of the second data lengths using the data stored in the other flash memory modules belonging to the same RAID group as the flash memory module storing the data having the address error; and

overwrites the data having the address error with the rebuilt data.

12. The storage system according to claim 7, wherein, when an address error occurs in a hard disk drive, the storage controller overwrites/corrects the data having the address error in units of the first data lengths.

13. The storage system according to claim 7, wherein any one of the protection codes includes write-time information.

14. The storage system according to claim 7, wherein any one of the protection codes includes an error detection code for protecting data of the second data length.

15. A data protection method performed in a storage system, the storage system having:

one or more flash memory modules each having one or more flash memory chips and a memory controller that controls reading/writing of data from/to the flash memory chips; and

a storage controller having cache memory that temporarily stores data read/written from/to one or more of the flash memory chips, and the memory area of one page including;

a memory area of a second length from/to which the storage controller can read/write data; and

a memory area for a redundant section,

the method comprising;

managing the data read/written from/to a flash memory chip in units of first data lengths in the cache memory;

creating a protection code enabling identification of address information for a write destination page, when writing data in a flash memory chip;

dividing the data in the cache memory, which is managed in units of first data lengths, into pieces so that the size of each set composed of a piece of the divided write data and its protection code will be of the second data length;

writing the respective sets of the pieces of the write data and protection codes in the flash memory chip in units of second data lengths; and

comparing the address information identified with the protection codes attached to the data read from the flash memory chip with the address information for the data that is intended to be read and checking whether there is an address error or not.