Fully-Buffered Memory-Module with Error-Correction Code (ECC) Controller in Serializing Advanced-Memory Buffer (AMB) that is transparent to Motherboard Memory Controller

• US 20080022186A1
• Filed: 07/24/2006
• Published: 01/24/2008
• Est. Priority Date: 07/24/2006
• Status: Active Grant

• Current Assignee: Kingston Technology Corporation
• Original Assignee: Kingston Technology Corporation
• Inventors: Co, Ramon S., Sun, David
• Granted Patent: US 7,487,428 B2
• Time in Patent Office: Days
• US Class Current: 714/763
• CPC Class Codes: G06F 11/1044 with specific ECC/EDC distribution
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports

Abstract

An error-correcting fully-buffered memory module can detect and correct some errors in data read from memory chips. An error correction code ECC controller is added to the Advanced Memory Buffer (AMB) on the memory module that fully buffers memory requests sent as serial packets. The error correction controller generates ECC bits for write data, and both the ECC bits and the write data are written to the memory chips by a DRAM controller in the AMB. During reads, an ECC checker generates a syndrome and can activate an error corrector to correct data or signal a non-correctable error. The corrected data is formed into serial packets sent back to the motherboard by the AMB. Configuration data for the ECC controller could be first programmed into a serial-presence-detect electrically-erasable programmable read-only memory (SPD-EEPROM) on the memory module, and then copied to error-correction configuration registers on the AMB during power-up.

Claims

1. An error-correcting fully-buffered memory module comprising:

a substrate having wiring traces formed thereon for conducting signals;

contact pads along a lower edge of the substrate, the contact pads for mating with a memory module socket on a motherboard;

a buffer chip mounted to the substrate;

a packet interface, in the buffer chip, for receiving incoming serial packets from the motherboard through the contact pads, and for generating outgoing serial packets for transmission through the contact pads to the motherboard;

memory chips mounted to the substrate, the memory chips having address, data, and control inputs that are isolated from the contact pads by the buffer chip;

a memory controller, in the buffer chip, for generating address, data, and control signals to the memory chips in response to the incoming serial packets received from the motherboard, and for reading read-data and error-correction code (ECC) bits from the memory chips in response to a read command extracted from the incoming serial packets; and

an error-correction controller, coupled to the memory controller, for generating the ECC bits from write-data extracted from incoming serial packets by the packet interface, and for checking the ECC bits read from the memory chips by the memory controller;

wherein the memory chips store the ECC bits generated by the error-correction controller and the write-data extracted by the packet interface,

whereby the ECC bits are locally generated by the error-correction controller and locally checked on the error-correcting fully-buffered memory module.

2. The error-correcting fully-buffered memory module of claim 1 wherein the error-correction controller further comprises an error corrector, activated when the error-correction controller detects an error in the read-data, for generating corrected read-data from the ECC bits and the read-data,

whereby read-data is corrected by the error corrector.

3. The error-correcting fully-buffered memory module of claim 2 further comprising:

error-correction configuration registers for storing an error-correction configuration of the error-correction controller.

4. The error-correcting fully-buffered memory module of claim 3 wherein the error-correction configuration stored in the error-correction configuration registers comprises a number of ECC bits generated from the write-data.

5. The error-correcting fully-buffered memory module of claim 3 wherein the error-correction configuration stored in the error-correction configuration registers comprises an enable indicator that disables the error-correction controller.

6. The error-correcting fully-buffered memory module of claim 3 further comprising:

a serial-presence-detect electrically-erasable programmable read-only memory (SPD-EEPROM), mounted to the substrate and connected to the contact pads, the SPD-EEPROM for storing the error-correction configuration.

7. The error-correcting fully-buffered memory module of claim 6 wherein the SPD-EEPROM is also for storing a configuration of the memory chips mounted on the substrate.

8. The error-correcting fully-buffered memory module of claim 6 wherein the error-correction configuration is stored in the SPD-EEPROM and in the error-correction configuration registers, the error-correction configuration remaining in the SPD-EEPROM when power is removed, the error-correction configuration being lost from the error-correction configuration registers when power is removed.

9. The error-correcting fully-buffered memory module of claim 3 wherein the contact pads carry module signals that comprise:

a differential clock and a reset signal that are applied to the buffer chip.

10. The error-correcting fully-buffered memory module of claim 9 wherein the module signals further comprise serial-presence-detect signals that comprise:

a serial-presence-detect clock;

a serial-presence-detect device address; and

serial-presence-detect data;

wherein the serial-presence-detect signals are applied to the buffer chip and to the SPD-EEPROM.

11. The error-correcting fully-buffered memory module of claim 3 wherein the buffer chip is an Advanced Memory Buffer (AMB) and wherein the contact pads comprise:

northbound-lane module inputs for connecting to northbound-lane inputs of the buffer chip, the northbound-lane module inputs being differential inputs for carrying data buffered from memory chips of downstream memory modules inserted into other memory module sockets on the motherboard;

northbound-lane module outputs for connecting to northbound-lane outputs of the buffer chip, the northbound-lane module outputs being differential outputs for carrying data buffered from the memory chips to a processor on the motherboard;

southbound-lane module inputs for connecting to southbound-lane inputs of the buffer chip, the southbound-lane module inputs being differential inputs for carrying data from the processor on the motherboard to the memory chips or to memory chips of downstream memory modules; and

southbound-lane module outputs for connecting to southbound-lane outputs of the buffer chip, the southbound-lane module outputs being differential outputs for carrying data from the processor to memory chips of downstream memory modules,

whereby the contact pads of the error-correcting fully-buffered memory module include northbound lanes and southbound lanes.

12. The error-correcting fully-buffered memory module of claim 11 wherein the error-correction configuration registers and the error-correction controller are integrated into the buffer chip with the packet interface and the memory controller.

13. The error-correcting fully-buffered memory module of claim 12 wherein the error-correction configuration registers comprise a non-volatile memory.

14. The error-correcting fully-buffered memory module of claim 3 wherein the memory chips comprise ECC memory chips that store the ECC bits and data memory chips that store the write-data extracted by the packet interface and generate the read-data in response to the memory controller,

whereby the ECC bits are stored in separate memory chips from the write-data.

15. An error-correcting advanced memory buffer comprising:

southbound input means for receiving packets over southbound serial lanes from a host processor;

southbound output means for transmitting packets over southbound serial lanes to a downstream memory module;

southbound re-timer means, coupled between the southbound input means and the southbound output means, for re-timing packets received by the southbound input means for transmission over the southbound output means;

northbound input means for receiving packets over northbound serial lanes from the downstream memory module;

northbound output means for transmitting packets over northbound serial lanes toward the host processor;

northbound re-timer means, coupled between the northbound input means and the northbound output means, for re-timing packets received by the northbound input means for transmission over the northbound output means;

memory controller means for generating local control signals to memory chips on a local memory module containing the error-correcting advanced memory buffer;

packet extract means, coupled between the southbound re-timer means and the memory controller means, for extracting commands, address and data from packets received over the southbound input means from the host processor;

packet generation means, coupled between the northbound re-timer means and the memory controller means, for generating packets for transmission over the northbound output means to the host processor;

wherein the packets generated by the packet generation means contain data read from the memory chips by the memory controller means;

error-correction configuration registers means for storing an error-correction configuration; and

error-correction controller means, coupled to the error-correction configuration registers means and to the memory controller means, for generating and checking error-correction code (ECC) bits, the error-correction controller means sending the ECC bits to the memory controller means, the error-correction controller means receiving the ECC bits from the memory controller means;

wherein the memory controller means is further for writing data and the ECC bits to the memory chips, and is further for reading data and the ECC bits from the memory chips;

whereby the ECC bits are locally generated, written, read, and checked by the error-correcting advanced memory buffer.

16. The error-correcting advanced memory buffer of claim 15 further comprising:

ECC generation means for generating the ECC bits from data extracted from packets by the packet extract means and written to the memory chips by the memory controller means; and

ECC checking means for checking the ECC bits and data read from the memory chips by the memory controller means.

17. The error-correcting advanced memory buffer of claim 16 further comprising:

ECC correcting means for correcting data read from the memory chips by the memory controller means when the ECC checking means detects a correctable error, the ECC correcting means generating replacement data.

18. The error-correcting advanced memory buffer of claim 17 wherein the packets generated by the packet generation means contain the replacement data generated by the ECC correcting means when the ECC checking means detects the correctable error.

19. The error-correcting advanced memory buffer of claim 18 further comprising:

multiplexer means for sending the replacement data to the packet generation means when the ECC checking means detects the correctable error, and for sending the data read by the memory controller means to the packet generation means when the ECC checking means does not detect the correctable error.

20. The error-correcting advanced memory buffer of claim 16 further comprising:

syndrome generation means, receiving the ECC bits and the data read from the memory chips by the memory controller means, for generating an error correction syndrome that indicates an error when the error correction syndrome has a non-zero value.

21. The error-correcting advanced memory buffer of claim 15 wherein the error-correction configuration identifies a number of ECC bits stored within the memory chips for each data word.

22. The error-correcting advanced memory buffer of claim 17 further comprising:

management-bus interface means for reading the error-correction configuration from a non-volatile memory over a management bus and for writing the error-correction configuration to the error-correction configuration registers means,

whereby the error-correction configuration is copied from the non-volatile memory to the error-correction configuration registers means.