Method and System for Improved Fault Tolerance in Distributed Customization Controls Using Non-Volatile Memory

• US 20080022371A1
• Filed: 11/09/2006
• Published: 01/24/2008
• Est. Priority Date: 05/24/2005
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Inventors: Chen, Iue-Shuenn, Chen, Xuemin
• Granted Patent: US 9,497,022 B2
• Time in Patent Office: Days
• US Class Current: 726/4
• CPC Class Codes: H04L 2209/12 Details relating to cryptographic hardware or logic circuitry
• CPC Class Codes: H04L 9/004 for fault attacks

Abstract

Certain aspects of a method and system for improved fault tolerance in distributed customization controls using non-volatile memory are disclosed. Aspects of one method may include mapping an input control signal to a plurality of input logic circuits within a security processor. A plurality of independent processing paths may be defined between each of the plurality of input logic circuits and an output logic circuit. Each of the plurality of independent processing paths may comprise one or more logic circuits. The input control signal may be routed via at least a portion of the plurality of independent processing paths. The portion of the plurality of independent processing paths may be combined in the output logic circuit to generate the input control signal.

Claims

1. A method for processing information in a communication system, the method comprising:

in a security processor, mapping an input control signal to a plurality of input logic circuits;

defining a plurality of independent processing paths between each of said plurality of input logic circuits and an output logic circuit, wherein each of said plurality of independent processing paths comprises at least one logic circuit; and

routing said input control signal via at least a portion of said plurality of independent processing paths.

2. The method according to claim 1, comprising combining said at least portion of said plurality of independent processing paths in said output logic circuit to generate said input control signal.

3. The method according to claim 2, comprising encrypting said input control signal before said mapping.

4. The method according to claim 3, comprising decrypting said encrypted input control signal after said combining.

5. The method according to claim 1, wherein each of said plurality of input logic circuits is at least one of:

a non-volatile memory, a secure flash electrically erasable programmable read only memory (EEPROM), a flash RAM, and a flip-flop within said security processor.

6. The method according to claim 1, wherein said output logic circuit is one of:

a non-volatile memory, a secure flash electrically erasable programmable read only memory (EEPROM), a flash RAM, and a flip-flop within said security processor.

7. The method according to claim 1, wherein said at least one logic circuit is at least one of:

a non-volatile memory, a secure flash electrically erasable programmable read only memory (EEPROM), a flash RAM, and a flip-flop within said security processor.

8. A machine-readable storage having stored thereon, a computer program having at least one code section for processing information in a communication system, the at least one code section being executable by a machine for causing the machine to perform steps comprising:

in a security processor, mapping an input control signal to a plurality of input logic circuits;

defining a plurality of independent processing paths between each of said plurality of input logic circuits and an output logic circuit, wherein each of said plurality of independent processing paths comprises at least one logic circuit; and

routing said input control signal via at least a portion of said plurality of independent processing paths.

9. The machine-readable storage according to claim 8, wherein said at least one code section comprises code for combining said at least portion of said plurality of independent processing paths in said output logic circuit to generate said input control signal.

10. The machine-readable storage according to claim 9, wherein said at least one code section comprises code for encrypting said input control signal before said mapping.

11. The machine-readable storage according to claim 10, wherein said at least one code section comprises code for decrypting said encrypted input control signal after said combining.

12. The machine-readable storage according to claim 8, wherein each of said plurality of input logic circuits is at least one of:

a non-volatile memory, a secure flash electrically erasable programmable read only memory (EEPROM), a flash RAM, and a flip-flop within said security processor.

13. The machine-readable storage according to claim 8, wherein said output logic circuit is one of:

a non-volatile memory, a secure flash electrically erasable programmable read only memory (EEPROM), a flash RAM, and a flip-flop within said security processor.

14. The machine-readable storage according to claim 8, wherein said at least one logic circuit is at least one of:

a non-volatile memory, a secure flash electrically erasable programmable read only memory (EEPROM), a flash RAM, and a flip-flop within said security processor.

15. A system for processing information, the system comprising:

a security processor in which an input control signal is mapped to a plurality of input logic circuits;

said security processor comprising a plurality of independent processing paths between each of said plurality of input logic circuits and an output logic circuit, wherein each of said plurality of independent processing paths comprises at least one logic circuit; and

said security processor enables routing of said input control signal via at least a portion of said plurality of independent processing paths.

16. The system according to claim 15, wherein said security processor enables combining of said at least portion of said plurality of independent processing paths in said output logic circuit to generate said input control signal.

17. The system according to claim 16, wherein said security processor enables encryption of said input control signal before said mapping.

18. The system according to claim 17, wherein said security processor enables decryption of said encrypted input control signal after said combining.

19. The system according to claim 15, wherein each of said plurality of input logic circuits is at least one of:

a non-volatile memory, a secure flash electrically erasable programmable read only memory (EEPROM), a flash RAM, and a flip-flop within said security processor.

20. The system according to claim 15, wherein said output logic circuit is one of:

a non-volatile memory, a secure flash electrically erasable programmable read only memory (EEPROM), a flash RAM, and a flip-flop within said security processor.

21. The system according to claim 15, wherein said at least one logic circuit is at least one of:

a non-volatile memory, a secure flash electrically erasable programmable read only memory (EEPROM), a flash RAM, and a flip-flop within said security processor.