SEMICONDUCTOR MEMORY DEVICE WITH MEMORY CELLS ON MULTIPLE LAYERS

• US 20080023747A1
• Filed: 07/13/2007
• Published: 01/31/2008
• Est. Priority Date: 07/25/2006
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: PARK, Ki-Tae, SIM, Jae-Sung, CHOI, Jung-Dal
• Granted Patent: US 7,812,390 B2
• Time in Patent Office: Days
• US Class Current: 257/314
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/41 of a memory region comprising a cell select transistor, e.g. NAND

Abstract

A semiconductor memory device includes a first substrate having at least one string including a first select transistor, a second select transistor, and first memory cells connected in series between the first and second select transistors of the first substrate. The semiconductor memory device further includes a second substrate having at least one string including a first select transistor, a second select transistor, and second memory cells connected in series between the first and second select transistors of the second substrate. The number of the first memory cells of the at least one string of the first substrate is different from a number of the second memory cells of the at least one string of the second substrate. For example, the number of second memory cells may be less than the number of first memory cells.

Claims

1. A semiconductor memory device comprising:

a first substrate having at least one string comprising a first select transistor, a second select transistor, and first memory cells connected in series between the first and second select transistors of the first substrate; and

a second substrate having at least one string comprising a first select transistor, a second select transistor, and second memory cells connected in series between the first and second select transistors of the second substrate,

wherein a number of the first memory cells of the at least one string of the first substrate is different from a number of the second memory cells of the at least one string of the second substrate.

2. The semiconductor memory device of claim 1, wherein the number of the second memory cells is less than the number of the first memory cells.

3. The semiconductor memory device of claim 1, wherein the first memory cells store M-bit data, and the second memory cells store at least one of single-bit data or N-bit data, where 2<

N<

M.

4. The semiconductor memory device of claim 1, wherein the first substrate comprises a silicon substrate and the second substrate comprises an epitaxial layer.

5. The semiconductor memory device of claim 1, wherein the first substrate comprises a first silicon substrate and the second substrate comprises a second silicon substrate opposing the first silicon substrate.

6. The semiconductor memory device of claim 1, wherein the semiconductor memory device comprises a NAND flash memory device.

7. The semiconductor memory device of claim 2, wherein a channel length of each of the second memory cells is longer than a channel length of each of the first memory cells.

8. The semiconductor memory device of claim 1, wherein the first memory cells comprise a first memory block and the second memory cells comprise a second memory block.

9. The semiconductor memory device of claim 1, further comprising:

a first plug connected to drains of the first select transistors;

a first switch transistor configured to connect the first plug to a bit line via a second plug;

a third plug connected to sources of the second select transistors; and

a second switch transistor configured to connect the third plug to a common source line.

10. The semiconductor memory device of claim 9, wherein the first switch transistor is activated when one of the strings is selected, and each of the first select transistors is activated when a corresponding string is selected.

11. The semiconductor memory device of claim 10, wherein the second select transistors and the second switch transistor are activated simultaneously.

12. The semiconductor memory device of claim 4, further comprising:

a peripheral circuit block formed on the first substrate and configured to control the first and second select transistors and the first and second memory cells of the strings.

13. A semiconductor memory device, comprising:

a first silicon substrate having at least one string comprising a first select transistor, a second select transistor, and memory cells connected in series between the first select transistor and the second select transistor;

a memory material layer having at least one string comprising a first select transistor, a second select transistor, and memory cells connected in series between the first select transistor and the second select transistor;

a first plug connected to drains of the first select transistors;

a first switch transistor configured to connect the first plug to a bit line via a second plug;

a third plug connected to sources of the second select transistors;

a second switch transistor configured to connect the third plug to a common source line; and

a peripheral circuit block, on the first silicon substrate, configured to control the first and second select transistors and the memory cells in each of the at least one first silicon substrate string and the at least one memory material layer string,

wherein a number of the memory cells in the at least one memory material layer string is less than a number of the memory cells in the at least one first silicon substrate string.

14. The semiconductor memory device of claim 13, wherein the memory cells in the at least one first silicon substrate string store M-bit data, and the memory cells in the at least one memory material layer string store single-bit data or N-bit data, where 2<

N<

M.

15. The semiconductor memory device of claim 13, wherein a channel length of each of the memory cells in the at least one memory material layer string is longer than a channel length of each of the memory cells in the at least one first silicon substrate string.

16. The semiconductor memory device of claim 13, wherein the memory cells in the at least one first silicon substrate string comprise a first memory block and the memory cells in the at least one memory material layer string comprise a second memory block.

17. The semiconductor memory device of claim 13, wherein the memory material layer comprises an epitaxial layer formed using an epitaxial process.

18. The semiconductor memory device of claim 13, wherein the semiconductor memory device comprises a NAND flash memory device.

19. The semiconductor memory device of claim 13, wherein the memory material layer comprises a second silicon substrate, the second silicon substrate opposing the first silicon substrate.