Multi-die DC-DC Boost Power Converter with Efficient Packaging

• US 20080023825A1
• Filed: 07/31/2007
• Published: 01/31/2008
• Est. Priority Date: 07/28/2006
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Chang, Allen, Hebert, Francois, Cheng, Wai-Keung Peter
• Granted Patent: US 7,808,102 B2
• Time in Patent Office: Days
• US Class Current: 257/724
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/16245 the item being metallic
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48472 the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
• CPC Class Codes: H01L 2224/73257 Bump and wire connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/4175 for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/41775 characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/4941 with a barrier layer between the silicon and the metal or metal silicide upper layer, e.g. Silicide/TiN/Polysilicon
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/7835 : with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 : Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/12032 : Schottky diode
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/30107 : Inductance

Abstract

A DC-DC boost converter in multi-die package is proposed having an output Schottky diode and a low-side vertical MOSFET controlled by a power regulating controller (PRC). The multi-die package includes a single die pad with the Schottky diode placed there on side by side with the vertical MOSFET. The PRC die is attached atop the single die pad via an insulating die bond. Alternatively, the single die pad is grounded. The vertical MOSFET is a top drain vertical N-channel FET, the substrate of Schottky diode die is its anode. The Schottky diode and the vertical MOSFET are stacked atop the single die pad. The PRC is attached atop the single die pad via a standard conductive die bond. The Schottky diode die can be supplied in a flip-chip configuration with cathode being its substrate. Alternatively, the Schottky diode is supplied with anode being its substrate without the flip-chip configuration.

Claims

1. An efficiently packaged multi-die semiconductor package for DC-DC boost converter application where the boost converter converts an unregulated DC input into a regulated DC output, the multi-die semiconductor package comprises:

A lead-frame with a single die pad;

a vertical MOSFET placed atop said die pad; and

a Schottky diode with its anode connected to the drain of the vertical MOSFET.

2. The multi-die semiconductor package of claim 1 further comprising a power regulating controller (PRC) for controlling the gate of the vertical MOSFET.

3. The multi-die semiconductor package of claim 1 wherein the drain of the vertical MOSFET is at its bottom surface and the Schottky diode is placed on the die pad side by side with the vertical MOSFET with the anode of the Schottky diode being at its bottom surface and electrically connected to the drain of the vertical MOSFET via the die pad.

4. The multi-die semiconductor package of claim 3 wherein the substrate of the Schottky diode die is its cathode with the Schottky diode die being packaged in a flip-chip configuration.

5. The multi-die semiconductor package of claim 2 wherein the PRC die is further attached to the single die pad via an insulating die bonding material whereby achieving a further reduced footprint of the single die pad with the vertical MOSFET, the Schottky diode and the PRC co-packaged atop the single die pad.

6. The multi-die semiconductor package of claim 5 wherein the substrate of the Schottky diode die is its cathode with the Schottky diode die being packaged in a flip-chip configuration.

7. The multi-die semiconductor package of claim 1 wherein the single die pad is grounded, the vertical MOSFET is a vertical N-channel FET, the substrate of the Schottky diode die is its anode and the top of the vertical MOSFET is its drain whereby the Schottky diode die and the vertical MOSFET die are co-packaged atop the single die pad in a stacked way with the Schottky diode die atop the vertical MOSFET die for minimized vertical MOSFET source inductance and easy heat sinking.

8. The multi-die semiconductor package of claim 7 wherein the PRC die is further attached to the single die pad via a standard conductive die bonding material whereby achieve a further reduced footprint of the single die pad with the vertical MOSFET, the Schottky diode and the PRC co-packaged atop the single die pad.

9. The multi-die semiconductor package of claim 2 wherein both the unregulated DC input and the regulated DC output are negative voltages hence the vertical MOSFET is a vertical P-channel FET, the substrate of the Schottky diode die is its cathode and the bottom of the vertical MOSFET is its drain whereby the Schottky diode die and the vertical MOSFET die are co-packaged side by side atop the single die pad.

10. The multi-die semiconductor package of claim 9 wherein the PRC die is further attached to the single die pad via an insulating die bonding material whereby achieve a further reduced footprint of the single die pad with the Schottky diode, the vertical MOSFET and the PRC co-packaged atop the single die pad.

11. The multi-die semiconductor package of claim 2 wherein both the unregulated DC input and the regulated DC output are negative voltages hence the vertical MOSFET is a vertical P-channel FET, the single die pad is grounded, the substrate of the Schottky diode die is its cathode and the top of the vertical MOSFET is its drain whereby the Schottky diode die and the vertical MOSFET die are co-packaged atop the single die pad in a stacked way with the Schottky diode die atop the vertical MOSFET die for minimized vertical MOSFET source inductance and easy heat sinking.

12. The multi-die semiconductor package of claim 11 wherein the PRC die is further attached to the single die pad via a standard conductive die bonding material whereby achieve a further reduced footprint of the single die pad with the Schottky diode, the vertical MOSFET and the PRC co-packaged atop the single die pad.