DISTORTION RESISTANT TOUCH-SENSITIVE DISPLAY PANEL

• US 20080024712A1
• Filed: 05/04/2007
• Published: 01/31/2008
• Est. Priority Date: 07/25/2006
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Dong-Gyu
• Granted Patent: US 7,649,605 B2
• Time in Patent Office: Days
• US Class Current: 349/144
• CPC Class Codes: G02F 1/13338 Input devices, e.g. touch panels
• CPC Class Codes: G02F 1/134363 for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G06F 3/0412 Digitisers structurally integrated in a display

Abstract

An array substrate includes a plurality of gate lines, a plurality of data lines, a plurality of thin-film transistors, a plurality of pixel electrodes, a plurality of common voltage lines and a plurality of common electrodes. The gate lines extend in a first direction. The data lines extend in a second direction substantially perpendicular to the first direction. The thin-film transistor is electrically connected to the gate line and the data line. The pixel electrode is formed in each of pixels defined by the gate lines and the data lines. The common electrode is electrically connected to the common voltage line. The horizontal alignment of the liquid crystal molecules is not changed by externally applied vertical touch pressure so that display quality is improved.

Claims

1. An array substrate comprising:

a plurality of gate lines extending in a first direction;

a plurality of data lines extending in a second direction substantially perpendicular to the first direction, the intersecting directions of the data lines and gate lines defining a plurality of pixels;

a plurality of thin-film transistors electrically connected to the gate lines and the data lines;

a pixel electrode electrically connected to each of the thin-film transistors;

a common voltage line extending in the second direction substantially parallel with the data lines; and

a common electrode formed in each of the pixels, electrically insulated from the pixel electrode, and electrically connected to the common voltage line.

2. The array substrate of claim 1, wherein the pixel electrode and the common electrode comprise a transparent conductive material.

3. The array substrate of claim 2, wherein the pixel electrode comprises:

a first main pixel electrode that extends in the first direction adjacent to one of the gate lines;

a second main pixel electrode extending in the first direction and spaced apart from the first main pixel electrode and adjacent to a consecutive one of the gate lines; and

a plurality of sub pixel electrodes disposed between the first and second main pixel electrodes to connect the first and second main pixel electrodes, the sub pixel electrodes being arranged in the first direction.

4. The array substrate of claim 3, further comprising an insulation layer formed between the common electrode and the pixel electrode, wherein the common electrode is disposed under the pixel electrode.

5. The array substrate of claim 4, wherein the common electrode is larger than the pixel electrode to cover the pixel electrode when viewed from a plan view.

6. The array substrate of claim 3, wherein the sub pixel electrode is symmetric with respect to a central line of the pixel which is substantially parallel with the second direction.

7. The array substrate of claim 6, wherein the sub pixel electrodes comprise:

a first sub pixel electrode that is adjacent to a first side of the central line, and is tilted at a predetermined angle to the second direction; and

a second sub pixel electrode that is adjacent to a second side of the central line, which is opposite to the first side, and is tilted by a predetermined angle to the second direction so that the first and second sub pixel electrodes are symmetric to the central line.

8. The array substrate of claim 3, further comprising:

a first insulation layer formed between the common electrode and the common voltage line;

a second insulation layer formed between the common voltage line and the pixel electrode;

a vertical connection electrode that is formed on the second insulation layer, and is electrically insulated from the pixel electrode; and

a contact hole formed through the first and second insulation layers, wherein the common voltage line is disposed in the common electrode, and the pixel electrode is disposed on the common voltage line, and the common voltage line has a common voltage connection portion electrically connected to the common electrode, and the vertical connection electrode electrically connects the common voltage connection portion to the common electrode through the contact hole.

9. The array substrate of claim 8, wherein the common voltage connection portion is symmetric with respect to a central line of the pixel, which is substantially parallel with the second direction.

10. The array substrate of claim 2, wherein the pixel electrode comprises:

a main pixel electrode that extends in the first direction, and is adjacent to one of the gate lines; and

a plurality of sub pixel electrodes protruding from the main pixel electrode toward a consecutive one of the gate lines, the sub pixel electrodes being arranged in the first direction.

11. The array substrate of claim 10, wherein the common electrode comprises:

a main common electrode that extends in the first direction, and is adjacent to a consecutive one of the gate lines; and

a plurality of sub common electrodes protruding from the main common electrode toward the main pixel electrode, the sub common electrodes being arranged in the first direction.

12. The array substrate of claim 11, wherein the common electrode is formed from a layer substantially the same as the pixel electrode.

13. The array substrate of claim 11, wherein the sub pixel electrodes are symmetric with respect to a central line of the pixel, which is substantially parallel with the second direction, and the sub common electrodes are symmetric with respect to the central line.

14. The array substrate of claim 13, wherein the sub pixel electrodes comprise:

a first sub pixel electrode that is adjacent to a first side of the central line, and is tilted at a predetermined angle to the second direction; and

a second sub pixel electrode that is adjacent to a second side of the central line, which is opposite to the first side, and is tilted at a predetermined angle to the second direction so that the first and second sub pixel electrodes are symmetric with respect to the central line, and the sub common electrodes comprise;

a first sub common electrode that is adjacent to a first side of the central line, and is substantially parallel with the first sub pixel electrode; and

a second sub common electrode that is adjacent to a second side of the central line, which is opposite to the first side, and is substantially parallel with the second sub pixel electrode.

15. The array substrate of claim 11, further comprising an insulation layer that is formed between the common electrode and the pixel electrode, and has a contact hole, wherein the common electrode is disposed under the pixel electrode, and is electrically connected to the common voltage line through the contact hole.

16. The array substrate of claim 2, further comprising a horizontal connection electrode to electrically connect adjacent common electrodes to each other.

17. The array substrate of claim 2, wherein each of the pixels has a rectangular shape, of which a first length in the first direction is longer than a second direction in the second direction.

18. The array substrate of claim 17, wherein the thin-film transistors electrically connected to one of data lines are alternatively adjacent to a first side of the data line and a second side of the data line opposite to the first side.

19. A display panel comprising:

an array substrate that comprises;

a plurality of gate lines extending in a first direction;

a plurality of data lines extending in a second direction substantially perpendicular to the first direction;

a plurality of thin-film transistors electrically connected to the gate line and the data line;

a pixel electrode formed in each of pixels defined by the gate lines and the data lines and electrically connected to each of the thin-film transistors;

a common voltage line extending in the second direction substantially parallel with the data line; and

a common electrode formed in each of the pixels electrically insulated from the pixel electrode and electrically connected to the common voltage line;

an opposite substrate facing the array substrate; and

a liquid crystal layer interposed between the array substrate and the opposite substrate and having liquid crystal molecules.

20. The display panel of claim 19, wherein the liquid crystal molecules of the liquid crystal layer are aligned substantially parallel with a surface of the array substrate, and are rotated by an electric field formed by the pixel electrode and the common electrode by a predetermined angle with being substantially parallel with the surface of the array substrate.