Self-Referenced Match-Line Sense Amplifier For Content Addressable Memories

• US 20080025073A1
• Filed: 07/14/2006
• Published: 01/31/2008
• Est. Priority Date: 07/14/2006
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: International Business Machines Corporation
• Inventors: Arsovski, Igor
• Granted Patent: US 7,724,559 B2
• Time in Patent Office: Days
• US Class Current: 365/149
• CPC Class Codes: G11C 15/04 using semiconductor elements
• CPC Class Codes: G11C 7/067 Single-ended amplifiers
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Abstract

A content addressable memory (CAM) device and process for searching a CAM. The CAM device includes a plurality of CAM cells, match-lines (MLs), search lines, and ML sense amplifiers. The ML sense amplifiers are capable of self-calibration to their respective thresholds to reduce effects of random device variation between adjacent sense amplifiers.

Claims

1. A content addressable memory (CAM) device comprising:

a plurality of CAM cells;

match-lines;

search lines; and

match-line sense amplifiers,

wherein the match-line sense amplifiers are capable of self-calibration to their respective thresholds to reduce effects of random device variation between adjacent sense amplifiers.

2. The CAM device in accordance with claim 1, further comprising switch units coupled to the match-lines to precharge each match-line to threshold of its associated match-line sense amplifiers.

3. The CAM device in accordance with claim 2, wherein the switching units comprise at least two FETs arranged in series between a supply voltage and the match-lines.

4. The CAM device in accordance with claim 3, further comprising inverters coupled to sense nodes located between the at least two FETs of the switching units, wherein outputs of the inverters are indicative of one of a match or a mismatch.

5. The CAM device in accordance with claim 4, wherein the FETs located between the sense nodes and the match-lines are turned off and on by elements coupled to an end of the match-line.

6. The CAM device in accordance with claim 2, wherein the thresholds correspond to thresholds of an element coupled to an end of the match-line.

7. The CAM device in accordance with claim 6, wherein the element comprises at least one inverter.

8. The CAM device in accordance with claim 6, wherein the element comprises a Schmitt trigger.

9. A process for searching a content addressable memory (CAM) device having match-lines and sense amplifiers, the process comprising:

precharging the match-lines to thresholds of their respective sense amplifiers.

10. The process in accordance with claim 9, wherein when the match-lines are precharged to thresholds, the process comprises:

interrupting precharging of match-lines; and

charging a sense node.

11. The process in accordance with claim 10, wherein, in the event of mismatches, the sense nodes are shorted to the match-lines.

12. The process in accordance with claim 10, wherein, in the event of matches, the sense nodes are isolated from the match-lines.

13. The process in accordance with claim 9, wherein a precharging signal is enabled until a threshold of a sense amplifier associated with a one-bit reference is attained.

14. The process in accordance with claim 9, wherein the thresholds of the respective sense amplifiers correspond to thresholds of at least one element coupled to the end of the match-lines.

15. The process in accordance with claim 14, wherein the element comprises at least one inverter.

16. The process in accordance with claim 14, wherein the element comprises a Schmitt trigger.

17. A content addressable memory (CAM) device comprising:

elements coupled to ends of match-lines, wherein each element has a respective threshold value; and

a device for charging the match-lines to the respective threshold values.

18. The CAM device in accordance with claim 17, further comprising switch units coupled to the match-lines to precharge the match-lines to the respective thresholds of the elements.

19. The CAM device in accordance with claim 18, wherein the switching units comprise at least two FETs arranged in series between a supply voltage and the match-lines.

20. The CAM device in accordance with claim 18, wherein the switching units comprise two FETs, and the device further comprises inverters coupled to sense nodes located between the two FETs, wherein outputs of the inverters are indicative of one of a match or a mismatch.