METHOD AND APPARATUS FOR GENERATING TEMPERATURE-COMPENSATED READ AND VERIFY OPERATIONS IN FLASH MEMORIES

• US 20080025121A1
• Filed: 10/02/2007
• Published: 01/31/2008
• Est. Priority Date: 08/26/2005
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Tanzawa, Toru
• Granted Patent: US 7,957,215 B2
• Time in Patent Office: Days
• US Class Current: 365/212
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

Methods and an apparatuses for generating a word-line voltage are disclosed. A word-line voltage generator includes a first current source, an adjustable current source, adjustable current sink, and a voltage converter, all operably coupled to a current sum node. The first current source generates a first current having a temperature coefficient substantially equal to a temperature coefficient of at least one bit cell. The adjustable current source generates a second current that is substantially independent of a temperature change. The adjustable current sink sinks a third current that is substantially independent of a temperature change. The voltage converter is configured for generating a word-line signal having a word-line voltage proportional to a reference current, wherein the reference current comprises the first current, plus the second current, and minus the third current.

Claims

1. A circuit for generating at least one word-line signal, comprising:

a first current source operably coupled to a current sum node and configured for generating a first current wherein an amount of the first current is substantially correlated to a temperature dependant threshold voltage of at least one storage cell; and

a voltage converter operably coupled to the current sum node and configured for generating at least one word-line signal having a word-line voltage proportional to the first current.

2. The circuit of claim 1, further comprising an adjustable current source operably coupled to the current sum node and configured for generating a second current that is substantially independent of a temperature change and wherein a reference current comprises a sum of the first current and the second current and the word-line voltage is proportional to the reference current.

3. The circuit of claim 2, wherein the first current source comprises a drive transistor with a source operably coupled to a voltage source, a drain operably coupled to the current sum node, and a gate operably coupled to a temperature compensated bias signal from a matching current controller.

4. The circuit of claim 3, wherein the matching current controller comprises:

a matched current source for generating a first current signal and a substantially equal second current signal;

at least one P-N junction element operably coupled between the first current signal and a ground; and

at least one resistance element operably coupled between the second current signal and the ground.

5. The circuit of claim 3, wherein the matching current controller comprises:

a matched current source configured to generate a first current signal and a substantially equal second current signal;

at least one first P-N junction element operably coupled between the first current signal and a ground; and

at least one resistance element and at least one second P-N junction element operably coupled in series between the second current signal and the ground.

6. The circuit of claim 3, wherein the matching current controller includes at least one non-volatile memory cell substantially similar to the storage cell to generate the temperature compensated bias signal from a biased current flowing through the at least one non-volatile memory cell.

7. The circuit of claim 6, wherein a control gate and a floating gate of the at least one non-volatile memory cell are operably coupled together.

8. The circuit of claim 3, wherein the matching current controller at least one transistor configured to substantially match temperature characteristics of the storage cell to generate the temperature compensated bias signal from a biased current flowing through at least one transistor.

9. The circuit of claim 2, further comprising an adjustable current sink operably coupled to the reference current, the voltage converter, and the adjustable current source and configured for sinking a third current that is substantially independent of the temperature change, wherein the word-line voltage is proportional to the sum of the first current and the second current, and the third current.

10. A circuit for generating a plurality of word-line signals, comprising:

a first current source for generating a reference current substantially correlated to a temperature dependant threshold voltage of at least one storage cell;

a voltage converter operably coupled to the reference current and configured for generating a word-line voltage proportional to the reference current; and

a row decoder configured for directing the word-line voltage to one of the plurality of word-line signals responsive to an address signal.

11. The circuit of claim 10, further comprising an adjustable current source operably coupled to the reference current and the voltage converter and configured for generating a second current substantially independent of a temperature change.

12. The circuit of claim 11, wherein the adjustable current source is configured to generate a first source current during a verify process and a second source current during a read process.

13. The circuit of claim 11, further comprising an adjustable current sink operably coupled to the reference current, the voltage converter, and the adjustable current source and configured for sinking a third current that is substantially independent of the temperature change, wherein the word-line voltage is proportional to the sum of the first current and the second current, and the third current.

14. The circuit of claim 13, wherein the adjustable current sink is configured to generate a first sink current during a verify process and a second sink current during a read process.

15. A semiconductor memory, comprising:

a word-line voltage generator to generate a plurality of word-line signals and comprising;

a first current source operably coupled to a current sum node and configured for generating a first current wherein a voltage derived from the first current comprises a temperature coefficient substantially equal to a temperature coefficient of at least one threshold voltage of a storage cell; and

a voltage converter operably coupled to the current sum node and configured for generating at least one of the plurality of word-line signals having a word-line voltage proportional to a reference current, wherein the reference current comprises the first current.

16. The semiconductor memory of claim 15, the circuit further comprising:

an adjustable current source operably coupled to the current sum node and configured for generating a second current that is substantially independent of a temperature change; and

an adjustable current sink operably coupled to the current sum node and configured for sinking a third current that is substantially independent of the temperature change;

wherein the reference current further comprises the sum of the first current, the second current, and the third current.

17. An electronic system, comprising:

at least one input device;

at least one output device;

a processor; and

a memory device comprising at least one semiconductor memory including at least one circuit configured to generate at least one word-line signal comprising;

a first current source operably coupled to a current sum node and configured for generating a first current with a temperature coefficient corresponding to to a temperature coefficient of a threshold voltage of a storage cell;

an adjustable current source operably coupled to the current sum node and configured for generating a second current that is substantially independent of a temperature change; and

a voltage converter operably coupled to the current sum node and configured for generating the at least one word-line signal.

18. The electronic system of claim 17, comprising:

wherein the adjustable current source is configured to generate a verify current during a verify process and a read current different from the verify current during a read process.

19. A method, comprising:

generating at least one temperature dependent word-line voltage for controlling at least one storage cell, the generating comprising;

generating a reference current with a temperature coefficient corresponding to a temperature coefficient of at least one threshold voltage of the at least one storage cell; and

converting the reference current to the at least one temperature dependent word-line voltage by directing the reference current through a voltage converter.

20. The method of claim 19, wherein generating the at least one temperature dependent word-line voltage further comprises:

generating a second current from an adjustable current source, wherein the second current is substantially independent of a temperature change; and

combining the second current with the reference current.

21. The method of claim 20, wherein generating the second current further comprises:

generating a first current level during a verify process; and

generating second current level during a read process.

22. The method of claim 20, wherein generating the second current further comprises generating the second current at a plurality of levels for multiple voltage levels of a multi-level storage cell programmed to indicate more than two states.

23. The method of claim 20, wherein generating the second current further comprises:

generating the second current to a verify current source level from a plurality of different current source levels during a verify process; and

generating the second current to a read current source level from a plurality of different current source levels during a read process.

24. The method of claim 20, further comprising:

generating an adjustable current sink, wherein the adjustable current sink is substantially independent of the temperature change; and

combining the adjustable current sink with the second current and the reference current.

25. The method of claim 24, wherein generating the adjustable current sink further comprises:

generating the adjustable current sink to a verify current sink level from a plurality of different current sink levels during a verify process; and

generating the adjustable current sink to a read current sink level from a plurality of different current sink levels during a read process.