MEMORY REFRESH SYSTEM AND METHOD

• US 20080025122A1
• Filed: 07/31/2006
• Published: 01/31/2008
• Est. Priority Date: 07/31/2006
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: MetaRAM Incorporated
• Inventors: Wang, David T., Smith, Michael John Sebastian, Weber, Frederick Daniel, Schakel, Keith R., Rajan, Suresh Natarajan
• Granted Patent: US 8,077,535 B2
• Time in Patent Office: Days
• US Class Current: 365/222
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40618 Refresh operations over multiple banks or interleaving
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers

Abstract

A system and method are provided. In response to the receipt of a refresh control signal, a plurality of refresh control signals is sent to the memory circuits at different times.

Claims

1. A method, comprising:

receiving a refresh control signal;

in response to the refresh control signal, sending a plurality of refresh control signals to a plurality of memory circuits as different times.

2. The method of claim 1, wherein the refresh control signal is received from a memory controller.

3. The method of claim 1, wherein a timing in which the refresh control signals are sent to the memory circuits is selected to minimize a current draw.

4. The method of claim 1, wherein the current draw includes a peak current draw.

5. The method of claim 1, wherein a timing in which the refresh control signals are sent to the memory circuit is selected to comply with a row refresh cycle time (tRFC) associated with each of the memory circuits.

6. The method of claim 1, wherein the sending is performed by an interface circuit for interfacing the plurality of memory circuits and a system.

7. The method of claim 6, wherein the interface circuit is operable to interface the memory circuits and the system for simulating at least one memory circuit with at least one aspect that is different from at least one aspect of at least one of the plurality of memory circuits.

8. The method of claim 7, wherein the interface circuit is operable to interface the memory circuits and the system for simulating at least one memory circuit with a first memory capacity that is greater than a second memory capacity of at least one of the plurality of memory circuits.

9. The method of claim 8, wherein a first row refresh cycle time (tRFC) associated with the at least one simulated memory circuit is greater than a second tRFC associated with each of the memory circuits.

10. The method of claim 9, wherein a timing in which the refresh control signals are sent to the memory circuits is selected to ensure that the second tRFC associated with each of the memory circuits is satisfied before the first tRFC elapses.

11. The method of claim 6, wherein a timing in which the refresh control signals are sent to the memory circuits is selected to minimize a current draw of the memory circuits.

12. The method of claim 1, wherein at least one first refresh control signal is sent to a first subset of the memory circuits at a firs time and at least one second refresh control signal is sent to a second subset of the memory circuits at a second time.

13. The method of claim 12, wherein at least one of the first subset and the second subset includes a single memory circuit.

14. The method of claim 12, wherein at least one of the first subset and the second subset includes a group of the memory circuits.

15. The method of claim 1, wherein the memory circuits each include dynamic random access memory (DRAM).

16. The method of claim 15, wherein the memory circuits each include a monolithic DRAM.

17. The method of claim 16, wherein the memory circuits are stacked.

18. The method of claim 1, wherein a single refresh control signal is sent to a plurality of the memory circuits.

19. The method of claim 1, wherein a plurality of the refresh control signals is sent to a plurality of the memory circuits.

20. A sub-system, comprising:

an interface circuit in communication with a plurality of memory circuits and a system, the interface circuit operable to send a plurality of refresh control signals to the memory circuits at different times.

21. A sub-system, comprising:

a plurality of memory circuits, and

an interface circuit in communication with the plurality of memory circuits and a system, the interface circuit operable to send a plurality of refresh control signals to the memory circuits at different times.