Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuits

• US 20080025123A1
• Filed: 09/20/2006
• Published: 01/31/2008
• Est. Priority Date: 07/31/2006
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: MetaRAM Incorporated
• Inventors: Rajan, Suresh Natarajan, Wang, David T., Weber, Frederick Daniel, Schakel, Keith R., Sebastian Smith, Michael John
• Granted Patent: US 7,392,338 B2
• Time in Patent Office: Days
• US Class Current: 365/227
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence

Abstract

A memory circuit power management system and method are provided. In use, an interface circuit is in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for autonomously performing a power management operation in association with at least a portion of the memory circuits.

Claims

1. A sub-system, comprising:

an interface circuit in communication with a plurality of memory circuits and a system, the interface circuit operable to interface the memory circuits and the system for autonomously performing a power management operation in association with at least a portion of the memory circuits.

2. The sub-system of claim 1, wherein the power management operation is initiated by the interface circuit autonomously.

3. The sub-system of claim 1, wherein the power management operation is initiated by at least one non-power management signal.

4. The sub-system of claim 3, wherein the non-power management signal includes a control signal.

5. The sub-system of claim 4, wherein the control signal is selected from the group consisting of an address signal and a data signal.

6. The sub-system of claim 4, wherein the control signal is associated with an operation selected from the group consisting of an activate operation, a precharge operation, a write operation, a read operation, a mode register write operation, a mode register read operation, and a refresh operation.

7. The sub-system of claim 1, wherein the power management operation is initiated in response to at least one non-power related state of one or more of the memory circuits.

8. The sub-system of claim 7, wherein the at least one state is selected from the group consisting of a predetermined combination of commands issued to the one or more of the memory circuits, a predetermined pattern of commands issued to the one or more of the memory circuits, and a predetermined absence of commands issued to the one or more of the memory circuits.

9. The sub-system of claim 1, wherein the interface circuit is further operable for simulating at least one virtual memory circuit.

10. The sub-system of claim 9, wherein the power management operation is performed in association with only a portion of the virtual memory circuit.

11. The sub-system of claim 9, wherein the at least one virtual memory circuit includes a single virtual memory circuit.

12. The sub-system of claim 1, wherein the power management operation includes a power saving operation.

13. The sub-system of claim 1, wherein the interface circuit is intelligent.

14. The sub-system of claim 1, wherein the interface circuit includes a circuit that is positioned on a dual in-line memory module (DIMM).

15. The sub-system of claim 1, wherein the interface circuit is selected from the group consisting of a buffer, a register, a memory controller, and an advanced memory buffer (AMB).

16. The sub-system of claim 1, wherein the interface circuit and the memory circuits take the form of a stack.

17. The sub-system of claim 16, wherein the stack includes a single interface circuit.

18. The sub-system of claim 16, wherein the stack includes a plurality of interface circuits.

19. A method, comprising:

interfacing a plurality of memory circuits and a system; and

autonomously performing a power management operation in association with at least a portion of the memory circuits.

20. A system, comprising:

a plurality of memory circuits; and

an interface circuit in communication with the memory circuits and a system, the interface circuit operable to interface the memory circuits and the system for autonomously performing a power management operation in association with at least a portion of the memory circuits.