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Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuits

  • US 20080025123A1
  • Filed: 09/20/2006
  • Published: 01/31/2008
  • Est. Priority Date: 07/31/2006
  • Status: Active Grant
First Claim
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1. A sub-system, comprising:

  • an interface circuit in communication with a plurality of memory circuits and a system, the interface circuit operable to interface the memory circuits and the system for autonomously performing a power management operation in association with at least a portion of the memory circuits.

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