Interface circuit system and method for performing power management operations utilizing power management signals

• US 20080025124A1
• Filed: 09/20/2006
• Published: 01/31/2008
• Est. Priority Date: 07/31/2006
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: MetaRAM Incorporated
• Inventors: Sebastian Smith, Michael John, Wang, David T., Weber, Frederick Daniel, Schakel, Keith R., Rajan, Suresh Natarajan
• Granted Patent: US 7,472,220 B2
• Time in Patent Office: Days
• US Class Current: 365/227
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence

Abstract

A memory circuit power management system and method are provided. In use, an interface circuit is in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for communicating a first number of power management signals to at least a portion of the memory circuits that is different from a second number of power management signals received from the system.

Claims

1. A sub-system, comprising:

an interface circuit in communication with a plurality of memory circuits and a system, the interface circuit operable to interface the memory circuits and the system for communicating a first number of power management signals to at least a portion of the memory circuits that is different from a second number of power management signals received from the system.

2. The sub-system of claim 1, wherein the power management signals include a clock enable signal.

3. The sub-system of claim 1, wherein the power management signals include a chip select signal.

4. The sub-system of claim 1, wherein a power management operation is initiated by at least one of the power management signals.

5. The sub-system of claim 4, wherein the power management operation includes an entry into a power down mode.

6. The sub-system of claim 4, wherein the power management operation includes an exit from a power down mode.

7. The sub-system of claim 1, wherein the memory circuits include at least one rank of memory circuits.

8. The sub-system of claim 1, wherein the first number of power management signals are utilized in a manner that is independent from each other, to power manage at least one portion of the memory circuits.

9. The sub-system of claim 1, wherein the interface circuit is further operable for simulating at least one virtual memory circuit.

10. The sub-system of claim 9, wherein a number of the at least one virtual memory circuit is less than the first number of power management signals.

11. The sub-system of claim 9, wherein the at least one virtual memory circuit includes a single virtual memory circuit.

12. The sub-system of claim 1, wherein the interface circuit includes a circuit that is positioned on a dual in-line memory module (DIMM).

13. The sub-system of claim 1, wherein the interface circuit is selected from the group consisting of a buffer, a register, a memory controller, and an advanced memory buffer (AMB).

14. The sub-system of claim 1, wherein the interface circuit and the memory circuits take the form of a stack.

15. The sub-system of claim 14, wherein the stack includes a single interface circuit.

16. The sub-system of claim 14, wherein the stack includes a plurality of interface circuits.

17. A method, comprising:

interfacing a plurality of memory circuits and a system;

receiving at least one power management signal from the system; and

communicating a different number of power management signals to at least a portion of the memory circuits.

18. A system, comprising:

a plurality of memory circuits; and

an interface circuit in communication with the memory circuits and a system, the interface circuit operable to interface the memory circuits and the system for communicating a first number of power management signals to at least a portion of the memory circuits that is different from a second number of power management signals received from the system.