NONVOLATILE MEMORY CELL COMPRISING A REDUCED HEIGHT VERTICAL DIODE

• US 20080026510A1
• Filed: 10/02/2007
• Published: 01/31/2008
• Est. Priority Date: 12/19/2002
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: S Herner, Steven Radigan
• Inventors: HERNER, S., Radigan, Steven
• Granted Patent: US 7,560,339 B2
• Time in Patent Office: Days
• US Class Current: 438/128
• CPC Class Codes: G11C 11/39 using thyristors or the avalanche or negative resistance type, e.g. PNPN, SCR, SCS, UJT
• CPC Class Codes: G11C 17/06 using diode elements G11C17/14 takes precedence
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 2213/77 Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/66272 Silicon vertical transistors H01L29/66242, H01L29/66257 and H01L29/66265 take precedence
• CPC Class Codes: H01L 29/732 Vertical transistors
• CPC Class Codes: H01L 29/868 PIN diodes
• CPC Class Codes: H10B 20/25 One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links

Abstract

A nonvolatile memory cell according to the present invention comprises a bottom conductor, a semiconductor pillar, and a top conductor. The semiconductor pillar comprises a junction diode, including a bottom heavily doped region, a middle intrinsic or lightly doped region, and a top heavily doped region, wherein the conductivity types of the top and bottom heavily doped region are opposite. The junction diode is vertically oriented and is of reduced height, between about 500 angstroms and about 3500 angstroms. A monolithic three dimensional memory array of such cells can be formed comprising multiple memory levels, the levels monolithically formed above one another.

Claims

1. A method for forming a monolithic three dimensional memory array, the method comprising:

i) forming a first memory level, the steps for forming the first memory level comprising;

a) forming a plurality of substantially parallel, substantially coplanar first conductors above a substrate;

b) forming a plurality of substantially parallel, substantially coplanar second conductors above the first conductors;

c) forming a plurality of first vertically oriented pillars, each first pillar comprising a first junction diode and disposed between one of the first conductors and one of the second conductors, wherein the first junction diodes have a first height between about 500 angstroms and about 3500 angstroms; and

ii) monolithically forming a second memory level on the first memory level.

2. The method of claim 1 wherein the height of the first junction diodes is between about 800 angstroms and about 3000 angstroms.

3. The method of claim 2 wherein the height of the first junction diodes is between about 1300 angstroms and about 2500 angstroms.

4. The method of claim 1 wherein the step of forming the first conductors comprises:

depositing a first conductive layer;

patterning and etching the first conductive layer into the first conductors;

depositing a first dielectric material on and between the first conductors; and

planarizing to expose the first conductors separated by the first dielectric material.

5. The method of claim 4 wherein the step of forming the first pillars comprises:

depositing a semiconductor layer stack on the first conductors and the first dielectric material; and

patterning and etching the semiconductor layer stack to form the first pillars.

6. The method of claim 5 wherein the step of forming the first pillars further comprises forming a top heavily doped region in each of the first pillars wherein the top heavily doped region is not doped by in situ doping.

7. The method of claim 6 wherein the top heavily doped region is doped by ion implantation, plasma immersion, gas source diffusion, or solid source diffusion.

8. The method of claim 7 wherein the top heavily doped region is doped by ion implantation.

9. The method of claim 8 wherein, during ion implantation, BF₂ ions are implanted.

10. The method of claim 5 wherein the step of forming the first pillars further comprises forming a bottom heavily doped region in each of the first pillars wherein the bottom heavily doped region is not doped by in situ doping.

11. The method of claim 10 wherein the bottom heavily doped region is doped by ion implantation, plasma immersion, gas source diffusion, or solid source diffusion.

12. The method of claim 11 wherein the bottom heavily doped region is doped by ion implantation.

13. The method of claim 12 wherein, during ion implantation, arsenic ions are implanted.

14. The method of claim 5 wherein the step of forming the first pillars further comprises forming a bottom heavily doped region in each of the first pillars by in situ doping.

15. The method of claim 1 wherein the step of forming a second memory level comprises:

forming a plurality of substantially parallel, substantially coplanar third conductors above the second conductors; and

forming a plurality of second vertically oriented pillars above the first pillars.

16. The method of claim 15 wherein each of the second pillars is disposed between one of the second conductors and one of the third conductors.

17. The method of claim 15 further comprising forming a plurality of substantially parallel, substantially coplanar fourth conductors above the third conductors, wherein each of the second pillars is disposed between one of the third conductors and one of the fourth conductors.

18. The method of claim 1 wherein the step of forming the first pillars comprises:

forming first bottom heavily doped regions doped by ion implantation having a first conductivity type;

forming first middle intrinsic or lightly doped regions immediately above the first bottom heavily doped regions; and

forming first top heavily doped regions immediately above the first middle intrinsic or lightly doped regions, the first top heavily doped regions doped by ion implantation and having a second conductivity type opposite the first conductivity type.

19. The method of claim 18 wherein the first bottom heavily doped regions are doped with arsenic ions.

20. The method of claim 18 wherein the first top heavily doped regions are doped with BF₂ ions.

21. The method of claim 18 wherein the first top heavily doped regions are doped with arsenic ions.

22. The method of claim 18 wherein the first bottom heavily doped regions are doped with BF₂ or boron ions.