METHOD OF FORMING AN ELECTRICALLY CONDUCTIVE LINE IN AN INTEGRATED CIRCUIT

• US 20080026564A1
• Filed: 02/23/2007
• Published: 01/31/2008
• Est. Priority Date: 07/31/2006
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Qing Su, Ruo, Werner, Thomas, Frohberg, Kai
• Granted Patent: US 7,622,391 B2
• Time in Patent Office: Days
• US Class Current: 438/637
• CPC Class Codes: H01L 21/76804 by forming tapered via holes
• CPC Class Codes: H01L 21/76805 the opening being a via or contact hole penetrating the underlying conductor
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76844 Bottomless liners
• CPC Class Codes: H01L 21/76847 the layer being positioned within the main fill metal
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method of forming a semiconductor structure comprises providing a semiconductor structure comprising a layer of a dielectric material provided over an electrically conductive feature. An opening is formed in the layer of dielectric material. The opening is located over the electrically conductive feature and has a first lateral dimension. A cavity is formed in the electrically conductive feature. The cavity has a second lateral dimension being greater than the first lateral dimension. The cavity and the opening are filled with an electrically conductive material.

Claims

1. A method of forming a semiconductor structure, comprising:

providing a semiconductor substrate comprising a layer of a dielectric material provided over an electrically conductive feature;

forming an opening in said layer of dielectric material, said opening being located over said electrically conductive feature and having a first dimension in a lateral direction, said lateral direction being substantially parallel to a surface of said layer of dielectric material;

forming a cavity in said electrically conductive feature, said cavity having a second dimension in said lateral direction, said second dimension being greater than said first dimension; and

filling said cavity and said opening with an electrically conductive material.

2. The method of claim 1, wherein said formation of said opening comprises performing an anisotropic etch process.

3. The method of claim 1, wherein said formation of said cavity comprises performing an isotropic etch process.

4. The method of claim 1, further comprising forming a barrier layer over at least one of a surface of said opening and a surface of said cavity.

5. The method of claim 1, wherein said cavity comprises a rounded bottom surface.

6. A method of forming a semiconductor structure, comprising:

providing a semiconductor substrate comprising a layer of a dielectric material provided over an electrically conductive feature, said layer of dielectric material comprising an opening being located over said electrically conductive feature;

performing a first etching process to form a recess in said electrically conductive feature, said first etching process being adapted to remove a material of the electrically conductive feature;

forming a protective layer over a first portion of said recess, a second portion of said recess not being covered by said protective layer; and

performing a second etching process, said second etching process being adapted to remove the material of the electrically conductive feature at a greater etch rate than a material of the protective layer.

7. The method of claim 6, wherein a degree of anisotropy of said first etching process is greater than a degree of anisotropy of said second etching process.

8. The method of claim 6, wherein said first etching process is an anisotropic etching process.

9. The method of claim 6, wherein said second etching process is an isotropic etching process.

10. The method of claim 6, wherein said first portion of said recess comprises a sidewall of said recess and wherein said second portion of said recess comprises a bottom of said recess.

11. The method of claim 6, wherein said formation of said protective layer comprises:

depositing a material layer comprising the material of the protective layer over said semiconductor structure;

performing an anisotropic etching process adapted to remove a portion of the material layer located over the second portion of the recess at a greater etch rate than a portion of the material layer located over the first portion of the recess; and

stopping said anisotropic etching process upon removal of said portion of said material layer located over said second portion of said recess.

12. A method of forming a semiconductor structure, comprising:

providing a semiconductor substrate comprising at least one layer of a dielectric material provided over an electrically conductive feature;

forming an opening in said at least one layer of dielectric material, said opening having a first portion and a second portion, said second portion being located at a greater distance from said electrically conductive feature than said first portion, said first portion having a first dimension in a lateral direction, said lateral direction being substantially parallel to a surface of said layer of dielectric material, said second portion having a second dimension in said lateral direction, said first dimension being greater than said second dimension; and

filling said opening with an electrically conductive material.

13. The method of claim 12, wherein said formation of said opening comprises performing a dry etching process adapted to simultaneously deposit a protective layer over sidewalls of already formed portions of said opening.

14. The method of claim 12, wherein said formation of said opening comprises:

performing a first etching process to form said second portion of said opening;

forming a protective layer over a sidewall of said second portion of said opening, at least a portion of a bottom of the second portion of the opening not being covered by said protective layer; and

performing a second etching process to form said first portion of said opening, said second etching process being adapted to remove a material of said at least one layer of dielectric material at a greater etch rate than a material of said protective layer.

15. The method of claim 14, wherein a degree of anisotropy of said first etching process is greater than a degree of anisotropy of said second etching process.

16. The method of claim 14, wherein said first etching process is anisotropic and said second etching process is isotropic.

17. The method of claim 14, wherein said formation of said protective layer comprises:

isotropically depositing a material layer comprising a material of said protective layer over said semiconductor substrate;

performing an anisotropic etching process adapted to remove a first portion of said material layer located over said sidewall of said second portion of said second opening at a smaller etch rate than a second portion of said material layer located on said bottom of said second portion of said opening; and

stopping said anisotropic etching process upon a removal of said second portion of said material layer.

18. The method of claim 12, wherein said at least one layer of dielectric material comprises a first layer of dielectric material and a second layer of dielectric material, said first layer of dielectric material being formed over said electrically conductive feature, said second layer of dielectric material being formed over said first layer of dielectric material, and wherein said formation of said opening comprises:

performing a first etching process to form said second portion of said opening in said second layer of dielectric material; and

after said first etching process, performing a second etching process to form said first portion of said opening in said first layer of dielectric material, wherein said second etching process is adapted to remove a material of said first layer of dielectric material, leaving said second layer of dielectric material substantially intact.

19. The method of claim 18, wherein a degree of anisotropy of said first etching process is greater than a degree of anisotropy of said second etching process.

20. The method of claim 18, wherein said first etching process is anisotropic and said second etching process is isotropic.