Defect probability calculating method and semiconductor device manufacturing method

• US 20080027576A1
• Filed: 07/20/2007
• Published: 01/31/2008
• Est. Priority Date: 07/20/2006
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Kyoh, Suigen
• Granted Patent: US 7,797,068 B2
• Time in Patent Office: Days
• US Class Current: 700/110
• CPC Class Codes: G03F 1/36 Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes

Abstract

A defect probability calculating method includes assuming a plurality of process conditions containing process variations caused in a process of forming a pattern on a substrate based on a design pattern, acquiring appearance probabilities of the respective process conditions, performing process simulation to predict a pattern to be formed on a substrate based on the design pattern for each of the process conditions, determining whether the pattern predicted by performing the process simulation satisfies preset criteria for each of the process conditions, and acquiring first probability by adding together appearance probabilities of the process conditions used for process simulation of patterns which are determined not to satisfy the preset criteria.

Claims

1. A defect probability calculating method comprising:

assuming a plurality of process conditions containing process variations caused in a process of forming a pattern on a substrate based on a design pattern;

acquiring appearance probabilities of the respective process conditions;

performing process simulation to predict a pattern to be formed on a substrate based on the design pattern for each of the process conditions;

determining whether the pattern predicted by performing the process simulation satisfies preset criteria for each of the process conditions; and

acquiring first probability by adding together appearance probabilities of the process conditions used for process simulation of patterns which are determined not to satisfy the preset criteria.

2. The method according to claim 1, wherein a process from said assuming the plurality of process conditions to said acquiring the first probability is performed for a specified portion extracted from the design pattern.

3. The method according to claim 2, wherein the specified portion is a provisionally rejected portion which is determined by previously performing process simulation for the design pattern.

4. The method according to claim 1, wherein a process from said assuming the plurality of process conditions to said acquiring the first probability is performed for each of a plurality of specified portions extracted from the design pattern, and

wherein the method further comprises one of first and second processes,

the first process comprising:

adding together the first probabilities acquired for the respective specified portions,

the second process comprising;

calculating a first value by subtracting the first probability from unity for each of the specified portions;

calculating a second value by multiplying together the first values calculated for the respective specified portions; and

subtracting the second value from unity.

5. The method according to claim 4, wherein the specified portion is a provisionally rejected portion which is determined by previously performing process simulation for the design pattern.

6. The method according to claim 1, wherein the process includes at least one of a photolithography process and etching process.

7. The method according to claim 1, wherein a process from said assuming the plurality of process conditions to said acquiring the first probability is performed for each of plural kinds of unit cells, and

wherein the method further comprises one of first and second processes,

the first process comprising;

acquiring the number of unit cells contained in a design pattern of a desired integrated circuit chip for each kind of unit cells;

calculating a product of the first probability and the number of unit cells for each kind of unit cells; and

calculating defect probability of the desired integrated circuit chip by adding together the products calculated for the respective kinds of unit cells,

the second process comprising;

acquiring the number of unit cells contained in a design pattern of a desired integrated circuit chip for each kind of unit cells;

calculating a first value by subtracting the first probability from unity for each kind of unit cells;

calculating a second value by multiplying the first value by itself by a number of times corresponding to the number of unit cells for each kind of unit cells;

calculating a third value by multiplying together the second values calculated for the respective kinds of unit cells; and

calculating defect probability of the desired integrated circuit chip by subtracting the third value from unity.

18. A semiconductor device manufacturing method comprising:

preparing a photomask having a mask pattern corresponding to a fixed design pattern based on the defect probability calculated by the method according to claim 1;

and

transferring the mask pattern on the photomask onto a photoresist on a semiconductor substrate.

19. The method according to claim 18, wherein the fixed design pattern is obtained when the defect probability is smaller than a preset value.

20. The method according to claim 18, wherein the defect probability is calculated for each of a plurality of design patterns by the method according to claim 1, and one of the design patterns which has the lowest defect probability is determined as the fixed design pattern.

8. A defect probability calculating method comprising:

dividing process variations occurring in a process of forming a pattern on a substrate based on a design pattern into a first process variation in which a central value of pattern dimensions shifts and a second process variation in which a pattern dimension varies depending on a pattern arrangement position;

assuming a plurality of process conditions containing the first process variations;

acquiring appearance probabilities of the respective process conditions;

performing process simulation for each of the process conditions with respect to the design pattern to predict a preset pattern;

acquiring a ratio at which the preset pattern predicted for each of the process conditions does not satisfy a preset dimensional condition due to the second process variation;

acquiring a product of the appearance probability and the ratio for each of the process conditions; and

acquiring first probability by adding together the products acquired for the respective process conditions.

9. The method according to claim 8, wherein said acquiring the ratio at which the preset pattern does not satisfy the preset dimensional condition includes predicting dimensional distribution of the preset pattern caused by the second process variation, and acquiring a ratio of a portion which does not satisfy preset criteria in the dimensional distribution.

10. The method according to claim 8, wherein a process from said dividing the process variations into the first process variation and the second process variation to said acquiring the first probability is performed for a specified portion extracted from the design pattern.

11. The method according to claim 10, wherein the specified portion is a provisionally rejected portion which is determined by previously performing process simulation for the design pattern.

12. The method according to claim 8, wherein a process from said dividing the process variations into the first process variation and the second process variation to said acquiring the first probability is performed for each of a plurality of specified portions extracted from the design pattern, and

wherein the method further comprises one of first and second processes,

the first process comprising:

adding together the first probabilities acquired for the respective specified portions,

the second process comprising;

calculating a first value by subtracting the first probability from unity for each of the specified portions;

calculating a second value by multiplying together the first values calculated for the respective specified portions; and

subtracting the second value from unity.

13. The method according to claim 12, wherein the specified portion is a provisionally rejected portion which is determined by previously performing process simulation for the design pattern.

14. The method according to claim 8, wherein the first process variation is based on a variation in a process parameter with time.

15. The method according to claim 8, wherein the second process variation is based on a local variation of a process parameter caused by noise.

16. The method according to claim 8, wherein the preset pattern is a photoresist pattern.

17. The method according to claim 8, wherein a process from said dividing the process variations into the first process variation and the second process variation to said acquiring the first probability is performed for each of plural kinds of unit cells, and

wherein the method further comprises one of first and second processes,

the first process comprising;

acquiring the number of unit cells contained in a design pattern of a desired integrated circuit chip for each kind of unit cells;

calculating a product of the first probability and the number of unit cells for each kind of unit cells; and

calculating defect probability of the desired integrated circuit chip by adding together the products calculated for the respective kinds of unit cells,

the second process comprising;

acquiring the number of unit cells contained in a design pattern of a desired integrated circuit chip for each kind of unit cells;

calculating a first value by subtracting the first probability from unity for each kind of unit cells;

calculating a second value by multiplying the first value by itself by a number of times corresponding to the number of unit cells for each kind of unit cells;

calculating a third value by multiplying together the second values calculated for the respective kinds of unit cells; and

calculating defect probability of the desired integrated circuit chip by subtracting the third value from unity.