SYSTEM AND METHOD FOR SIMULATING A DIFFERENT NUMBER OF MEMORY CIRCUITS

• US 20080027702A1
• Filed: 07/31/2006
• Published: 01/31/2008
• Est. Priority Date: 06/24/2005
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: MetaRAM Incorporated
• Inventors: Wang, David T., Smith, Michael John Sebastian, Weber, Frederick Daniel, Schakel, Keith R., Rajan, Suresh Natarajan
• Granted Patent: US 8,359,187 B2
• Time in Patent Office: Days
• US Class Current: 703/21
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40618 Refresh operations over multiple banks or interleaving
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers

Abstract

A system and method are provided for simulating a different number of memory circuits. Included is an interface circuit in communication with a first number of memory circuits and a system. Such interface circuit is operable to interface the memory circuits and the system for simulating at least one memory circuit of a second number. Further, the interface circuit interfaces a majority of address or control signals of the memory circuits.

Claims

1. A sub-system, comprising:

an interface circuit in communication with a first number of memory circuits and a system, the interface circuit operable to interface the memory circuits and the system for simulating at least one memory circuit of a second number,

wherein the interface circuit interfaces a majority of address or control signals of the memory circuits.

2. The sub-system of claim 1, wherein the second number is less than the first number.

3. The sub-system of claim 2, wherein the second number is one.

4. The sub-system of claim 1, wherein the interface circuit is operable to interface the memory circuits and the system for simulating at least one memory circuit with a first memory capacity that is greater than a second memory capacity of at least one of the plurality of memory circuits.

5. The sub-system of claim 1, wherein the interface circuit interfaces all of the address or control signals of the memory circuits.

6. The sub-system of claim 1, wherein the interface circuit interfaces a majority of the address signals of the memory circuits.

7. The sub-system of claim 1, wherein the interface circuit interfaces a majority of the control signals of the memory circuits.

8. The sub-system of claim 1, wherein the simulation includes an electrical simulation.

9. The sub-system of claim 1, wherein the simulation includes a logical simulation.

10. The sub-system of claim 1, wherein the interface circuit includes a buffer chip.

11. The sub-system of claim 1, wherein the interface circuit is positioned on a dual in-line memory module (DIMM).

12. The sub-system of claim 11, wherein the DIMM includes a small outline-DIMM (SO-DIMM).

13. The sub-system of claim 11, wherein the DIMM includes a fully buffered-DIMM (FB-DIMM).

14. The sub-system of claim 11, wherein the DIMM includes an un-buffered DIMM.

15. The sub-system of claim 11, wherein the DIMM includes a registered-DIMM (R-DIMM).

16. The sub-system of claim 1, wherein the memory circuits each include dynamic random access memory (DRAM).

17. The sub-system of claim 16, wherein the memory circuits each include a monolithic DRAM.

18. The sub-system of claim 17, wherein the memory circuits are stacked.

19. The sub-system of claim 17, wherein the memory circuits and the interface circuit are stacked.

20. The sub-system of claim 1, wherein the simulation includes a protocol simulation.

21. A method, comprising:

interfacing a majority of address or control signals of a first number of memory circuits and a system; and

simulating at least one memory circuit of a second number.

22. A system, comprising:

a first number of memory circuits; and

an interface circuit operable to interface the memory circuits and a system for simulating at least one memory circuit of a second number;

wherein the interface circuit interfaces a majority of address or control signals of the memory circuits.