MEMORY CIRCUIT SIMULATION SYSTEM AND METHOD WITH REFRESH CAPABILITIES

• US 20080027703A1
• Filed: 10/26/2006
• Published: 01/31/2008
• Est. Priority Date: 07/31/2006
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: MetaRAM Incorporated
• Inventors: Wang, David T., Smith, Michael John Sebastian, Weber, Frederick Daniel, Schakel, Keith R., Rajan, Suresh Natarajan
• Granted Patent: US 8,280,714 B2
• Time in Patent Office: Days
• US Class Current: 703/21
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40618 Refresh operations over multiple banks or interleaving
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers

Abstract

A system and method are provided including an interface circuit in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the plurality of memory circuits and the system for simulating at leas one memory circuit with at least one aspect that is different from at least one aspect of at least one of the plurality of memory circuits. The interface circuit is further operable to control refreshing of the plurality of memory circuits.

Claims

1. A memory apparatus for use in a data system, the memory apparatus comprising:

a plurality of physical memory circuits having a physical attribute;

an interface circuit coupled to communicate with the physical memory circuits, and couplable to communicate with the data system, the interface circuit including,

means for simulating a simulated memory circuit having a simulated attribute which is different than the physical attribute of the physical memory circuits, and for providing to the data system an interface to the simulated memory circuit including the simulated attribute, and

means for controlling refreshing of the physical memory circuits.

2. The memory apparatus of claim 1, wherein the physical attribute comprises:

a physical signal.

3. The memory apparatus of claim 2, wherein the physical signal comprises at least one of:

an address signal;

a control signal; and

a data signal.

4. The memory apparatus of claim 1, wherein the physical attribute comprises:

a capacity.

5. The memory apparatus of claim 4, wherein the capacity comprises:

a memory capacity.

6. The memory apparatus of claim 5, wherein:

the memory capacity relates to a number of the physical memory circuits.

7. The memory apparatus of claim 1, wherein the physical attribute comprises:

a logical interface.

8. The memory apparatus of claim 1, wherein the physical attribute comprises:

a timing.

9. The memory apparatus of claim 8, wherein:

the timing relates to a latency.

10. The memory apparatus of claim 9, wherein the timing comprises at least one of:

a row address to column address latency (tRCD);

a row precharge latency (tRP);

an active to precharge latency (tRAS);

a row cycle time (tRC);

a refresh latency (tRFC); and

a column address strobe (CAS) latency.

11. The memory apparatus of claim 1, wherein:

the means for controlling refreshing is responsive to a refresh control signal.

12. The memory apparatus of claim 11, wherein:

the memory apparatus is coupled to receive the refresh control signal from a memory controller of the data system.

13. The memory apparatus of claim 11, wherein the interface circuit further comprises:

means for sending a plurality of refresh control signals to respective physical memory circuits at different times.

14. The memory apparatus of claim 13, wherein:

the means for sending the plurality of refresh control signals is adapted to select the different times in order to reduce a current draw of the plurality of physical memory circuits.

15. The memory apparatus of claim 1 wherein:

the physical memory circuits are symmetrical.

16. The memory apparatus of claim 1 wherein:

the physical memory circuits are asymmetrical.

17. The memory apparatus of claim 1, wherein:

at least one of the physical memory circuits is integrated with the interface circuit.

18. The memory apparatus of claim 1, wherein:

at least one of the physical memory circuits is separate from the interface circuit.

19. A method of operating a memory apparatus which is coupled to a plurality of physical memory circuits and to a system, the physical memory circuits having a physical characteristic, the method comprising:

simulating a memory device having a simulated characteristic which is different than the physical characteristic;

providing to the system an interface to the simulated memory device; and

controlling refreshing of the physical memory circuits in conjunction with the simulated memory interface.

20. The method of claim 19 wherein the physical memory circuits have a physical latency, and wherein:

the simulated characteristic comprises a simulated latency; and

the controlling refreshing comprises refreshing the physical memory circuits during a time provided by a difference between the physical latency of the physical memory circuits and the simulated latency of the simulated memory device.

21. An apparatus comprising:

a system;

a plurality of physical memory circuits;

an interface circuit coupled to the system and to the physical memory circuits, wherein the interface circuit is operable to provide to the system an interface of a simulated memory device which differs from the physical memory circuits, and to control refreshing of the physical memory circuits in an manner different than the simulated memory device interface indicates to the system.

22. The apparatus of claim 21 wherein:

the simulated memory device interface indicates a first refresh latency; and

the physical memory circuits have a second refresh latency which is shorter than the first refresh latency.