Memory-mapped buffers for network interface controllers

• US 20080028103A1
• Filed: 07/26/2006
• Published: 01/31/2008
• Est. Priority Date: 07/26/2006
• Status: Active Grant

• Current Assignee: Valtrus Innovations Limited (f/k/a Dolya Holdco 9 Limited) (Key Patent Innovations Limited)
• Original Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Inventors: Oertli, Erwin, Schlansker, Michael Steven
• Granted Patent: US 9,137,179 B2
• Time in Patent Office: Days
• US Class Current: 709/250
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/901 using storage descriptor, e.g. read or write pointers
• CPC Class Codes: H04L 49/9063 Intermediate storage in different physical parts of a node or terminal

Abstract

Systems and methods for providing network interface controllers (NICs) with memory-mapped buffers are described. A processing system includes a plurality of processing cells, each including at least one processor and at least one system memory. A NIC is associated with each of the processing cells for transmitting and receiving data between the processing cells. Each of the cells further includes a memory interconnect to which the NIC is directly connected and the NIC includes at least one memory-mapped buffer.

Claims

1. A processing system comprising:

a plurality of processing cells, each of said processing cells including at least one processor and at least one system memory; and

a network interface controller (NIC) associated with each of said plurality of processing cells for transmitting and receiving data between said processing cells;

wherein each of said plurality of cells further includes a memory interconnect to which said NIC is directly connected and said NIC includes at least one memory-mapped buffer.

2. The system of claim 1 wherein said NIC further comprises:

wherein said at least one memory-mapped buffer is one of a memory-mapped transmit buffer and a memory-mapped receive buffer, wherein a portion of said at least one system memory is allocated for memory-mapping said at least one of a memory-mapped transmit buffer and a memory-mapped receive buffer.

3. The system of claim 2, wherein said at least one of said memory-mapped transmit buffer and said memory-mapped receive buffer is a circular queue having a head pointer and a tail pointer and further wherein current values of said head pointer and said tail pointer are mapped to predetermined locations within said system memory.

4. The system of claim 3, wherein said at least one of a memory-mapped transmit buffer and a memory-mapped receive buffer is a memory mapped receive buffer and further wherein said at least one processor compares a previously stored value of one of said head pointer and said tail pointer with a respective current value of said one of said head pointer and said tail pointer as a polling mechanism for said memory-mapped receive buffer.

5. The system of claim 3, wherein said at least one processor compares a previously stored value of at least one of said head pointer and said tail pointer with a respective current value of said at least one of said head pointer and said tail pointer to determine whether to unpin one or more pages in said system memory.

6. The system of claim 1, further comprising:

an I/O interconnect through which I/O devices communicate with said at least one processor and at least one system memory; and

an I/O adapter for connecting said I/O interconnect to said memory interconnect.

7. The system of claim 1, wherein said system memory further comprises a delivery instruction database and wherein said at least one of a memory-mapped transmit buffer and a memory-mapped receive buffer is a memory-mapped receive buffer, such that said at least one processor operates to forward data received in said memory-mapped receive buffer in accordance with an instruction from said delivery instruction database.

8. The system of claim 7, wherein said processor performs a direct memory access (DMA) transfer of said data in accordance with said instruction from said delivery instruction database.

9. The system of claim 6, further comprising:

an operating system application running on said at least one processor;

a kernel-mode helper thread operating under said operating system which can access operating system data structures and communicate directly with a said NIC,

wherein said kernel-mode helper thread performs a pin, transmit/receive data, unpin cycle without interrupting said I/O interconnect.

10. A method for communicating data in a processing system comprising the steps of:

providing a plurality of processing cells, each of said processing cells including at least one processor and at least one system memory; and

transmitting and receiving data between said processing cells via a network interface controller (NIC) associated with each of said plurality of processing cells;

wherein each of said plurality of cells further includes a memory interconnect to which said NIC is directly connected and said NIC includes at least one memory-mapped buffer.

11. The method of claim 10 further comprising the step of:

allocating a portion of said at least one system memory for memory-mapping said at least one memory-mapped buffer.

12. The method of claim 11, wherein said at least one memory-mapped buffer is a circular queue having a head pointer and a tail pointer and further comprising the step of:

mapping current values of said head pointer and said tail pointer to predetermined locations within said system memory.

13. The method of claim 12, wherein said at least one memory-mapped buffer is a memory mapped receive buffer and further comprising the step of:

comparing, by said at least one processor, a previously stored value of one of said head pointer and said tail pointer with a respective current value of said one of said head pointer and said tail pointer as a polling mechanism for said memory-mapped receive buffer.

14. The method of claim 12, further comprising the step of:

comparing, by said at least one processor, a previously stored value of at least one of said head pointer and said tail pointer with a respective current value of said at least one of said head pointer and said tail pointer to determine whether to unpin one or more pages in said system memory.

15. The method of claim 10, further comprising the step of:

connecting I/O devices with said at least one processor and said at least one system memory via an I/O interconnect; and

connecting said I/O interconnect to said memory interconnect via an I/O adapter.

16. The method of claim 10, wherein said system memory further comprises a delivery instruction database and wherein said at least one memory-mapped buffer is a memory-mapped receive buffer, said method further comprising the step of:

forwarding, by said at least one processor, data received in said memory-mapped receive buffer in accordance with an instruction from said delivery instruction database.

17. The method of claim 16, further comprising the step of:

performing a direct memory access (DMA) transfer of said data in accordance with said instruction from said delivery instruction database.

18. The method of claim 16, further comprising the steps of:

running an operating system application on said at least one processor;

operating a kernel-mode helper thread under said operating system which can access operating system data structures and communicate directly with a said NIC; and

performing, by said kernel-mode helper thread, a pin, transmit/receive data, unpin cycle without interrupting said I/O interconnect.

19. The method of claim 10 further comprising the steps of:

performing page pinning actions associated with data transmission in said NIC;

determining fixed, physical addresses for pinned pages;

initiating a direct memory access (DMA) transfer from said pinned pages;

detecting completion of said data transmission by recognizing a change in a value associated with a memory-mapped transmit buffer; and

unpinning pages from which data has been transmitted.

20. The method of claim 10 further comprising the steps of:

performing page pinning actions associated with data reception in said NIC;

determining fixed, physical addresses for pinned pages;

initiating a direct memory access (DMA) to copy received data to said pinned pages;

detecting completion of said data reception by recognizing a change in a value associated with a memory-mapped receive buffer; and

unpinning pages after data has been delivered from said pinned pages to another location.